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10 Commits

Author SHA1 Message Date
Quentin Dian
112fba974c
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147) 
Per #80143, we can remove the extra line break when there is no
instruction.
 2024-02-01 22:10:52 +08:00
Fangrui Song
9e9907f1cf
[AMDGPU,test] Change llc -march= to -mtriple= (#75982) 
Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
 2024-01-16 21:54:58 -08:00
Matt Arsenault
56303223ac llvm-reduce: Don't assert on functions which don't track liveness 
Use the query that doesn't assert if TracksLiveness isn't set, which
needs to always be available. We also need to start printing liveins
regardless of TracksLiveness.
 2022-06-07 10:00:25 -04:00
Matt Arsenault
574ca03ef3 AMDGPU: Remove some invalid kill flags in tests 
These killed registers need to be live out of the block but the
verifier wasn't catching it.
 2022-05-04 00:05:15 +01:00
Matt Arsenault
5dfe4b7cf2 AMDGPU: Regenerate test checks 2022-05-04 00:05:15 +01:00
Stanislav Mekhanoshin
78fbd1aa3d [AMDGPU] Process any power of 2 in optimizeCompareInstr 
Differential Revision: https://reviews.llvm.org/D109201
 2021-09-02 17:39:17 -07:00
Stanislav Mekhanoshin
2cfda6a691 [AMDGPU] Fold immediates in the optimizeCompareInstr 
Peephole works before the first SIFoldOperands so most of
the immediates are in registers.

Differential Revision: https://reviews.llvm.org/D109186
 2021-09-02 17:23:26 -07:00
Stanislav Mekhanoshin
832c87b4fb [AMDGPU] Use S_BITCMP0_* to replace AND in optimizeCompareInstr 
These can be used for reversed conditions if result of the AND
is unused except in the compare:

s_cmp_eq_u32 (s_and_b32 $src, 1), 0 => s_bitcmp0_b32 $src, 0
s_cmp_eq_i32 (s_and_b32 $src, 1), 0 => s_bitcmp0_b32 $src, 0
s_cmp_eq_u64 (s_and_b64 $src, 1), 0 => s_bitcmp0_b64 $src, 0
s_cmp_lg_u32 (s_and_b32 $src, 1), 1 => s_bitcmp0_b32 $src, 0
s_cmp_lg_i32 (s_and_b32 $src, 1), 1 => s_bitcmp0_b32 $src, 0
s_cmp_lg_u64 (s_and_b64 $src, 1), 1 => s_bitcmp0_b64 $src, 0

Differential Revision: https://reviews.llvm.org/D109099
 2021-09-02 09:38:01 -07:00
Stanislav Mekhanoshin
f3645c792a [AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr 
Differential Revision: https://reviews.llvm.org/D109082
 2021-09-01 15:59:12 -07:00
Stanislav Mekhanoshin
bf77b11277 [AMDGPU] Introduce optimizeCompareInstr 
The following patterns are currently handled:

s_cmp_eq_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_eq_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_eq_u64 (s_and_b64 $src, 1), 1 => s_and_b64 $src, 1
s_cmp_ge_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_ge_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_lg_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
s_cmp_lg_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
s_cmp_lg_u64 (s_and_b64 $src, 1), 0 => s_and_b64 $src, 1
s_cmp_gt_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
s_cmp_gt_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1

Differential Revision: https://reviews.llvm.org/D109031
 2021-09-01 15:57:05 -07:00