246 Commits

Author SHA1 Message Date
Dmitry Nechitaev
3c6502933e
[ELF][Objcopy] Dont corrupt symbol table when --update-section is called for ELF files (#170462)
Fixes #168060
2026-01-14 09:44:02 +00:00
ZhaoQi
aa0ba7e01d
[LoongArch][Driver] Allow -gsplit-dwarf and -mrelax to be used together (#175727)
Benefit from https://github.com/llvm/llvm-project/pull/166597 and
https://github.com/llvm/llvm-project/pull/164813, DWARF fission is now
compatible with linker relaxation.

Similar to RISC-V, this commit allows `-gsplit-dwarf` and `-mrelax` to
be used together.

A new test `relax_dwo_ranges.ll` same as RISC-V is also added.
2026-01-13 20:05:48 +08:00
Cullen Rhodes
752d7f590e Clear release notes 2026-01-13 09:34:22 +00:00
Nerixyz
b22c149770
[LLDB] Mention MSVC STL formatters in release notes (#175527)
We already had a few MSVC STL formatters at the last release, but we
postponed the release note entry until they support PDB. The formatters
now support PDB.

There are still some left (see
https://github.com/llvm/llvm-project/issues/24834#issuecomment-3049291996),
but the most common types are formatted.
2026-01-12 16:34:33 +01:00
Philipp Tomsich
43138d6272
[Aarch64] Add support for Ampere1C core (#175442)
This patch adds initial support for the ARMv9.2+ Ampere1C core.
2026-01-12 09:52:23 +01:00
Sam Elliott
1eebd2a42e
[RISCV] Mark Xqccmp as not experimental (#175066) 2026-01-10 07:50:29 -08:00
Dan Gohman
597ffbe09d
Rename wasm32-wasi to wasm32-wasip1. (#165345)
This adds code to recognize "wasm32-wasip1", "wasm32-wasip2", and
"wasm32-wasip3" as explicit targets, and adds a deprecation warning when
the "wasm32-wasi" target is used, pointing users to the "wasm32-wasip1"
target.

Fixes #165344.

I'm filing this as a draft PR for now, as I've only just now proposed to
make this change in #165344.
2026-01-10 00:09:06 +00:00
Jay Foad
6f5c214928
[TableGen] Remove deprecated !getop and !setop (#175155)
They have been deprecated for more than five years in favor of !getdagop
and !setdagop. See https://reviews.llvm.org/D89814.
2026-01-09 15:16:09 +00:00
Tamir Duberstein
e39ddab2bc
[llvm-c] Add LLVMParseIRInContext2 (#174085)
This new function is the same as LLVMParseIRInContext except it doesn't
take ownership of the memory buffer. This fixes a wart that has been in
place since 5ebb7b311223bcd21d2b3d25413d1edacefcc63d changed the
underlying internal API to avoid taking ownership.

Reduce nesting in the implementation of LLVMParseIRInContext (now
LLVMParseIRInContext2) as well.

Update examples, OCaml bindings, and tests including plugging some
pre-existing memory leaks. OCaml bindings have renamed `parse_ir` to
`parse_ir_bitcode_or_assembly` to provoke compilation failures in
downstream code; this is intentional as this function now requires the
memory buffer to be disposed by the caller.
2026-01-08 16:50:05 +00:00
Trevor Gross
db26ce5c55
[PowerPC] Change half to use soft promotion rather than PromoteFloat (#152632)
On PowerPC targets, `half` uses the default legalization of promoting to
a `f32`. However, this has some fundamental issues related to inability
to round trip. Resolve this by switching to the soft legalization, which
passes `f16` as an `i16`.

The PowerPC ABI Specification does not define a `_Float16` type, so the
calling convention changes are acceptable.

Fixes the PowerPC part of
https://github.com/llvm/llvm-project/issues/97975
Fixes the PowerPC part of
https://github.com/llvm/llvm-project/issues/97981
2026-01-08 15:35:01 +01:00
Trevor Gross
4903c6260c
[WebAssembly] Change half to use soft promotion rather than PromoteFloat (#152833)
The default `half` legalization, which Wasm currently uses, does not
respect IEEE conventions: for example, casting to bits may invoke a lossy
libcall, meaning soft float operations cannot be correctly implemented.
Change to the soft promotion legalization which passes `f16` as an `i16`
and treats each `half` operation as an individual
f16->f32->libcall->f32->f16 sequence.

Of note in the test updates are that `from_bits` and `to_bits` are now
libcall-free, and that chained operations now round back to `f16` after
each step.

Fixes the wasm portion of
https://github.com/llvm/llvm-project/issues/97981
Fixes the wasm portion of
https://github.com/llvm/llvm-project/issues/97975
Fixes: https://github.com/llvm/llvm-project/issues/96437
Fixes: https://github.com/llvm/llvm-project/issues/96438
2026-01-08 15:07:59 +01:00
Sudharsan Veeravalli
520ba7d0e5
[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
Version 0.13 of the Xqci Qualcomm uC Vendor Extension has been marked as
frozen. We've had assembler support for this since LLVM20 and code
generation support since LLVM21. I think we have enough coverage in the
code base to mark the extension as non-experimental.
2025-12-24 07:10:47 +05:30
Ruoyu Qiu
60418dd8c2
[llvm-objdump] Fix memory leak in mcpuHelp() (#172594)
Reland #165661 with fix for memory leak.

The call to `DummyTarget->createMCSubtargetInfo` within `mcpuHelp()`
returns a pointer that is not subsequently freed, leading to a memory
leak. Use `std::unique_ptr` to ensure the memory is released
automatically.

Original description:

---

Currently --mcpu=help and --mattr=help only produce help out when
disassembling. This patch specialises these cases to always print the
requested help.

If --triple is specified, the help text will be derived from the
specified target. Otherwise, it will be derived from the target of the
first input file.

Fixes: https://github.com/llvm/llvm-project/issues/150567
2025-12-17 10:10:54 +00:00
Qinkun Bao
e04ce74fe2
Revert "[llvm-objdump] Support --mcpu=help/--mattr=help without -d" (#172586)
Reverts llvm/llvm-project#165661

Break
https://lab.llvm.org/buildbot/#/builders/24/builds/15720
https://lab.llvm.org/buildbot/#/builders/55/builds/21517
2025-12-17 03:13:03 +00:00
Ruoyu Qiu
516dd2b70b
[llvm-objdump] Support --mcpu=help/--mattr=help without -d (#165661)
Currently `--mcpu=help` and `--mattr=help` only produce help out when
disassembling. This patch specialises these cases to always print the
requested help.

If `--triple` is specified, the help text will be derived from the
specified target. Otherwise, it will be derived from the target of the
first input file.

Fixes: #150567

---------

Signed-off-by: Ruoyu Qiu <cabbaken@outlook.com>
Co-authored-by: James Henderson <James.Henderson@sony.com>
2025-12-16 14:56:20 +00:00
dcandler
23f967ada0
[AArch64] Add support for C1 CPUs (#171124)
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra

For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra

Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/

Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/

Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/

Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
2025-12-16 14:54:27 +00:00
Jonas Devlieghere
8d59cca1ab
[lldb] Add WebAssembly platform (#171507)
This PR adds a platform for WebAssembly. Heavily inspired by Pavel's
QemuUser, the platform lets you configure a WebAssembly runtime to run a
Wasm binary.

For example, the following configuration can be used to launch binaries
under the WebAssembly Micro Runtime (WARM):

```
settings set -- platform.plugin.wasm.runtime-args --heap-size=1048576
settings set -- platform.plugin.wasm.port-arg -g=127.0.0.1:
settings set -- platform.plugin.wasm.runtime-path /path/to/iwasm-2.4.0
```

With the settings above, you can now launch a binary directly under
WAMR:

```
❯ lldb simple.wasm
(lldb) target create "/Users/jonas/wasm-micro-runtime/product-mini/platforms/darwin/build/simple.wasm"
Current executable set to '/Users/jonas/wasm-micro-runtime/product-mini/platforms/darwin/build/simple.wasm' (wasm32).
(lldb) b main
Breakpoint 1: 2 locations.
(lldb) r
Process 1 launched: '/Users/jonas/wasm-micro-runtime/product-mini/platforms/darwin/build/simple.wasm' (wasm32)
2 locations added to breakpoint 1
[22:28:05:124 - 16FE27000]: control thread of debug object 0x1005e9020 start

[22:28:05:124 - 16FE27000]: Debug server listening on 127.0.0.1:49170

the module name is /Users/jonas/wasm-micro-runtime/product-mini/platforms/darwin/build/simple.wasm
Process 1 stopped
* thread #1, name = 'nobody', stop reason = breakpoint 1.3
    frame #0: 0x40000000000001d3 simple.wasm`main at simple.c:8:7
   5    }
   6
   7    int main() {
-> 8      int i = 1;
   9      int j = 2;
   10     return add(i, j);
   11   }
(lldb)
```
2025-12-11 11:12:26 -08:00
Alexis Engelke
6813f8f037
[IR] Don't store switch case values as operands
SwitchInst case values must be ConstantInt, which have no use list.
Therefore it is not necessary to store these as Use, instead store them
more efficiently as a simple array of pointers after the uses, similar
to how PHINode stores basic blocks.

After this change, the successors of all terminators are stored
consecutively in the operand list. This is preparatory work for
improving the performance of successor access.

Add new C API functions so that switch case values remain accessible
from bindings for other languages.

While this could also be achieved by merely changing the order of
operands (i.e., first all successors, then all constants), doing so
would increase the asymptotic runtime of addCase from O(1) to O(n)
(i.e., adding n cases would be O(n^2)), because it would need to shift
all constants by one slot. Having null/invalid operands is also a bad
idea and would cause much more breakage.

Pull Request: https://github.com/llvm/llvm-project/pull/170984
2025-12-11 18:38:39 +01:00
anjenner
27651133e2
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw (#105553)
These both perform conditional subtraction, returning the minuend and
zero respectively, if the difference is negative.
2025-12-09 23:13:33 +00:00
David Spickett
b3a5870c64 [llvm][docs] Add a release note for LLDB "version -v"
Added by #170772.
2025-12-09 16:00:18 +00:00
Nikita Popov
ec1ea0a4ca
[llvm-c] Deprecate functions working on the global context (#163979)
One of the most common mistakes when working with the LLVM C API is to
mix functions that work on the global context and those that work on an
explicit context. This often results in seemingly nonsensical errors
because types from different contexts are mixed.

We have considered the APIs working on the global context to be obsolete
for a long time already, and do not add any new APIs using the global
context. However, the fact that these still exist (and have shorter
names) continues to cause issues.

This PR proposes to deprecate these APIs, with intent to remove them at
some point in the future.

RFC:
https://discourse.llvm.org/t/rfc-deprecate-c-api-functions-using-the-global-context/88639
2025-12-08 08:29:48 +00:00
Vitaly Buka
90e3ac6c55
Revert "[IR] Don't store switch case values as operands" (#170962)
Reverts llvm/llvm-project#166842

Breaks Mips LLVM tests, and LLD on bots.
See llvm/llvm-project#166842
2025-12-06 03:09:58 +00:00
Alexis Engelke
f26360f215
[IR] Don't store switch case values as operands (#166842)
SwitchInst case values must be ConstantInt, which have no use list.
Therefore it is not necessary to store these as Use, instead store them
more efficiently as a simple array of pointers after the uses, similar
to how PHINode stores basic blocks.

After this change, the successors of all terminators are stored
consecutively in the operand list. This is preparatory work for
improving the performance of successor access.
2025-12-05 17:25:23 +01:00
peter mckinna
0ba73fb0f0
[llvm-c] Add LLVMConstFPFromBits() API (#164381)
This change adds the ability to create a 128 bit floating point value
from 2 64 bit integer values.
Some language frontends have already parsed a floating point string into
a proper 128 bit quad value
and need to get the llvm value directly.
2025-12-04 11:34:19 +01:00
daniilavdeev
3098bfe7d9
[llvm][Docs] Add release notes about dwarf fission with relaxations (#169871) 2025-12-02 14:47:17 +03:00
Matthew Nagy
9e25a423d0
[TySan] Make TySan compatible with UBSan (#169036) 2025-11-28 12:34:33 +00:00
Matthew Nagy
560b83c0cd
[TySan][Clang] Add clang flag to use tysan outlined instrumentation a… (#166170)
…nd update docs
2025-11-21 14:54:49 +00:00
Jonathan Thackray
8cc93c490d
[AArch64] Remove FEAT_TME assembly and ACLE support (#167687)
The Transactional Memory Extension (TME) was introduced as part of
Armv9-A but has not been adopted by the ecosystem. This mirrors what
Arm has observed with similar extensions in other architectures.

Therefore, remove FEAT_TME assembly and ACLE code from llvm, because
support for TME has now been officially withdrawn, as noted here:

```
   FEAT_TME is withdrawn from all future versions of Arm®
   Architecture Reference Manual for A-profile architecture.
```

referenced in Known Issue D24093, documented here:
   https://developer.arm.com/documentation/102105/lb-05/
2025-11-14 12:11:55 +00:00
Jonathan Thackray
40a9e3482a
[AArch64][llvm] Add support for Permission Overlay Extension 2 (FEAT_S1POE2) (#164912)
Add assembly/disassembly support for AArch64 `FEAT_S1POE2` (Stage 1
Permission Overlay Extension 2), as blogged about here:

* https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/future-architecture-technologies-poe2-and-vmte

and as documented here:

* https://developer.arm.com/documentation/109697/2025_09/Future-Architecture-Technologies

Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>
2025-11-14 10:24:26 +00:00
Tomer Shafir
35ffe10349
[opt] Add --save-stats option (#167304)
This patch adds a Clang-compatible --save-stats option to opt, to
provide an easy to use way to save LLVM statistics files when working
with opt on the middle end.

This is a follow up on the addition to `llc`:
https://github.com/llvm/llvm-project/pull/163967

Like on Clang, one can specify --save-stats, --save-stats=cwd, and
--save-stats=obj with the same semantics and JSON format. The
pre-existing --stats option is not affected.

The implementation extracts the flag and its methods into the common
`CodeGen/CommandFlags` as `LLVM_ABI`, using a new registration class to
conservatively enable opt-in rather than let all tools take it. Its only
needed for llc and opt for now. Then it refactors llc and adds support
for opt.
2025-11-13 16:03:28 +02:00
Jonathan Thackray
603ba84fb4
[AArch64][llvm] Add instructions for FEAT_MOPS_GO (#164913)
Add the following `FEAT_MOPS_GO` instructions:
  * `SETGOP`, `SETGOM`, `SETGOE`
  * `SETGOPN`, `SETGOMN`, `SETGOEN`
  * `SETGOPT`, `SETGOMT`, `SETGOET`
  * `SETGOPTN`, `SETGOMTN`, `SETGOETN`

as blogged about here:
*
https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/future-architecture-technologies-poe2-and-vmte

and as documented here:
*
https://developer.arm.com/documentation/109697/2025_09/Future-Architecture-Technologies
2025-11-12 21:14:30 +00:00
Daniel Thornburgh
c9ff2df8c3
[IR] "modular-format" attribute for functions using format strings (#147429)
A new InstCombine transform uses this attribute to rewrite calls to a
modular version of the implementation along with llvm.reloc.none
relocations against aspects of the implementation needed by the call.

This change only adds support for the 'float' aspect, but it also builds
the structure needed for others.

See issue #146159
2025-11-11 11:52:56 -08:00
Tomer Shafir
96a52893ca
[tools][llc] Add --save-stats option (#163967)
This patch adds a Clang-compatible `--save-stats` option, to provide an
easy to use way to save LLVM statistics files when working with llc on
the backend.

Like on Clang, one can specify `--save-stats`, `--save-stats=cwd`, and
`--save-stats=obj` with the same semantics and JSON format.

The implementation uses 2 methods `MaybeEnableStats` and
`MaybeSaveStats` called before and after `compileModule` respectively
that externally own the statistics related logic, while `compileModule`
is now required to return the resolved output filename via an output
param.

Note: like on Clang, the pre-existing `--stats` option is not affected.
2025-11-09 14:11:53 +02:00
Daniel Thornburgh
50daf4d600
Add @llvm.reloc.none intrinsic to LLVM release notes (#166805)
This declares PR #147427.
2025-11-06 17:16:47 +00:00
Alexandre Ganea
421ba7fbb5
[llvm-config] Add new flag --quote-paths to optionally quote and escape paths (#103397)
If any of the printed paths by llvm-config contain quotes, spaces,
backslashes or dollar sign characters, these paths will be quoted and
escaped, but only if using `--quote-paths`. The previous behavior is
retained for compatibility and `--quote-paths` is there to acknowledge
the migration to the new behavior.

Following discussion in #76304

Fixes #28117

Superseeds https://github.com/llvm/llvm-project/pull/97305

I could also do what @tothambrus11 suggests in
https://github.com/llvm/llvm-project/pull/97305#issuecomment-2282847990
but that makes all Windows paths quoted & escaped since they all contain
backslashes.
2025-11-01 17:19:21 +00:00
nerix
287ca7b243
[LLDB] Use native PDB reader by default (#165363)
All PDB tests now pass when compiled without DIA on Windows, so they
pass with the native reader.

With this PR, the default reader changes to the native reader.
The plan is to eventually remove the DIA reader (see
https://discourse.llvm.org/t/rfc-removing-the-dia-pdb-plugin-from-lldb/87827
and #114906).

For now, DIA can be used by setting `plugin.symbol-file.pdb.reader` to
`dia` or by setting `LLDB_USE_NATIVE_PDB_READER=0` (mostly undocumented,
but used in tests).
2025-10-29 16:51:38 +01:00
Jonathan Thackray
7ac2900718
[ARM][AArch64] Introduce the Armv9.7-A architecture version (#163154)
This introduces the Armv9.7-A architecture version, including the
relevant command-line option for -march.

More details about the Armv9.7-A architecture version can be found at:
   * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2025
   * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
   * https://developer.arm.com/documentation/ddi0602/2025-09/

Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
2025-10-23 23:12:58 +01:00
jofrn
5c666f559c
IR/Verifier: Allow vector type in atomic load and store (#148893)
Vector types on atomics are assumed to be invalid by the verifier. However,
this type can be valid if it is lowered by codegen.
2025-10-23 01:33:57 -04:00
Nikita Popov
573ca36753
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
The `masked.load`, `masked.store`, `masked.gather` and `masked.scatter`
intrinsics currently accept a separate alignment immarg. Replace this
with an `align` attribute on the pointer / vector of pointers argument.

This is the standard representation for alignment information on
intrinsics, and is already used by all other memory intrinsics. This
means the signatures now match llvm.expandload, llvm.vp.load, etc.
(Things like llvm.memcpy used to have a separate alignment argument as
well, but were already migrated a long time ago.)

It's worth noting that the masked.gather and masked.scatter intrinsics
previously accepted a zero alignment to indicate the ABI type alignment
of the element type. This special case is gone now: If the align
attribute is omitted, the implied alignment is 1, as usual. If ABI
alignment is desired, it needs to be explicitly emitted (which the
IRBuilder API already requires anyway).
2025-10-20 08:50:09 +00:00
Mikołaj Piróg
22a2a82054
[X86] Add support for Nova Lake (#163552)
Add support for Nova Lake, per Intel Architecture Instruction Set
Extensions Programming Reference rev. 59
(https://cdrdv2.intel.com/v1/dl/getContent/671368)
2025-10-16 14:58:23 +02:00
Ebuka Ezike
097f1e7625
[lldb] Do not stop the process on SIGWINCH by default. (#163182)
SIGWINCH is sent when the terminal window size changes.. Most people
debugging do not want the process on this signal.

When using lldb-dap, the user may be using an integrated terminal and
may resize the pane/window mulitple times when debugging. this causes
the signal to be sent multiple times. It gets in the way.

The process ignores this signal by default
2025-10-15 17:19:51 +01:00
Mikołaj Piróg
0e6557d71c
[X86] Add support for Wildcat Lake (#163214)
Add support for Wildcat Lake, per Intel Architecture Instruction Set
Extensions Programming Reference rev. 59
(https://cdrdv2.intel.com/v1/dl/getContent/671368)
2025-10-15 10:36:20 +02:00
Haohai Wen
e8f721e621
[clang][docs] Update doc and release note for probe instrumentation (#162606)
-fpseudo-probe-for-profiling is supported for COFF in #123870.
llvm-profgen supports decoding pseudo probe in #158207.

This PR updates release note and adds an example to use it in
UsersManual.rst.
2025-10-14 09:02:43 +08:00
Jonas Devlieghere
578c03f7e5
[lldb] Support OSC escape codes for native progress (#162162)
This PR adds support for emitting the OSC `9;4` sequences to show a GUI
native progress bar.

There's a limited number of terminal emulators that support this, so for
now this requires explicit opt-in through a setting. I'm reusing the
existing `show-progress` setting, which became a NOOP with the
introduction of the statusline. The option now defaults to off.

Implements #160369
2025-10-13 13:48:41 -07:00
AMS21
9f552ee6d2
[LLVM-C] Allow LLVMGetVolatile to work with any kind of Instruction (#163060)
Allow LLVMGetVolatile() to work with any kind of Instruction, rather
than only memory instructions that accept a volatile flag. For
instructions that can never be volatile, the function now return false
instead of asserting. This matches the behavior of
`Instruction::isVolatile()` in the C++ API.
2025-10-13 10:35:21 +02:00
AMS21
01f4510118
[LLVM-C] Upstream LLVMGetOrInsertFunction from rustc (#162235)
Add `LLVMGetOrInsertFunction` to the C API as a thin wrapper over
`Module::getOrInsertFunction`, upstreamed from
[rustc](d773bd07d6/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp (L203)).
It provides a single-call way to get or create a function declaration,
avoiding `LLVMGetNamedFunction` + `LLVMAddFunction` and is more
idiomatic.
2025-10-07 14:49:39 +00:00
Marco Elver
c7274fce2f
[AllocToken] Introduce AllocToken instrumentation pass (#156838)
Introduce `AllocToken`, an instrumentation pass designed to provide
tokens to memory allocators enabling various heap organization
strategies, such as heap partitioning.

Initially, the pass instruments functions marked with a new attribute
`sanitize_alloc_token` by rewriting allocation calls to include a token
ID, appended as a function argument with the default ABI.

The design aims to provide a flexible framework for implementing
different token generation schemes. It currently supports the following
token modes:

- TypeHash (default): token IDs based on a hash of the allocated type
- Random: statically-assigned pseudo-random token IDs
- Increment: incrementing token IDs per TU

For the `TypeHash` mode introduce support for `!alloc_token` metadata:
the metadata can be attached to allocation calls to provide richer
semantic
information to be consumed by the AllocToken pass. Optimization remarks
can be enabled to show where no metadata was available.

An alternative "fast ABI" is provided, where instead of passing the
token ID as an argument (e.g., `__alloc_token_malloc(size, id)`), the
token ID is directly encoded into the name of the called function (e.g.,
`__alloc_token_0_malloc(size)`). Where the maximum tokens is small, this
offers more efficient instrumentation by avoiding the overhead of
passing an additional argument at each allocation site.

Link: https://discourse.llvm.org/t/rfc-a-framework-for-allocator-partitioning-hints/87434 [1]

---

This change is part of the following series:
  1. https://github.com/llvm/llvm-project/pull/160131
  2. https://github.com/llvm/llvm-project/pull/156838
  3. https://github.com/llvm/llvm-project/pull/162098
  4. https://github.com/llvm/llvm-project/pull/162099
  5. https://github.com/llvm/llvm-project/pull/156839
  6. https://github.com/llvm/llvm-project/pull/156840
  7. https://github.com/llvm/llvm-project/pull/156841
  8. https://github.com/llvm/llvm-project/pull/156842
2025-10-07 13:30:07 +02:00
Aiden Grossman
7ff6973f1a
[lit] Remove support for %T
This patch removes support for %T from llvm-lit. For now we mark the
test unresolved and add an error message noting the substitution is
deprecated. This is exactly the same as the error handling for other
substitution failures. We intend to remove support for the nice error
message once 22 branches as users should have moved over by the they are
upgrading to v23.

Reviewers: petrhosek, jh7370, ilovepi, pogo59, cmtice

Reviewed By: cmtice, jh7370, ilovepi

Pull Request: https://github.com/llvm/llvm-project/pull/160028
2025-09-26 19:06:09 -07:00
Rux124
d34f738562
[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514)
Add MC layer support for Andes XAndesVSIntH extension. The spec is
available at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
2025-09-23 06:03:30 +00:00
Jim Lin
e747223c03
[RISCV] Implement MC support for Zvfofp8min extension (#157014)
This patch adds MC support for Zvfofp8min
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.
2025-09-19 07:49:31 +00:00