440857 Commits

Author SHA1 Message Date
Florian Hahn
8086b0c8a8
[ConstraintElim] Drop bail out for scalable vectors after using getTrue
ConstantInt::getTrue/getFalse can materialize scalable vectors with all
lanes true/false.
2022-11-03 19:05:45 +00:00
Mats Petersson
b36d678b8e [flang]Fix build failure in tests
After submitting the DataLayout fix, some tests fail when they didn't
before. This has to do with the target essentially being ignored when
these tests were run earlier, as the --target x86-unknown-linux-gnu
only has to be correctly formed to be accepted.

Now the target triple is actually being used to get the targetmachine
earlier - before MLIR is generated - so the test that has a valid target
but not available on the platform fails.

Fix is to require x86 registered target when running those tests.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D137335
2022-11-03 18:53:23 +00:00
Nathan Chancellor
74bace2dfe
Revert "[AArch64] Improve codegen for shifted mask op"
This reverts commit b4e1466c35d3ca3e04244e8e8b4ffaf0784d6d37.

This causes a crash while building the Linux kernel. See the original
Phabricator review for a reduced C and LLVM IR reproducer.
2022-11-03 11:33:50 -07:00
Mingming Liu
5d7fdf67f6 [NFC][AArch64]Precommit test for D135102
- Run auto updater for 'trunc-to-tbl.ll' and 'build-pair-isel.ll'
- Add the motivating test of D135102 to 'bitfield-insert.ll'

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D137296
2022-11-03 10:49:58 -07:00
Jason Molenda
fd2065b70f Have GetSupportedArchitectures report all supported arches
PlatformDarwinKernel::GetSupportedArchitectures returns a list
of architectures that are possible for this platform; it was using
a compile-time check for the debug host to decide the list of arches
that were valid.  This was copied from a codepath doing native process
debugging, and was clearly wrong for kernel debugging, but it had
not happened to cause problems so it went unnoticed for a long time.

Small NFC change to the logging messages of Target::SetArchitecture
to make them a little more explicit about how the architecture is
being modified/replaced.

Differential Revision: https://reviews.llvm.org/D137301
rdar://101690111
2022-11-03 10:46:48 -07:00
Emilio Cota
7e133eb49b [mlir][bufferize] Add filterFn option to BufferResultsToOutParams
This allows users to restrict the transformation to a
subset of the functions in a module.

For example, a user might want to apply the transformation to
a module's entry point, but not to the calls in the module
because those calls might refer to external C functions outside
of their control.

Reviewed By: springerm, nicolasvasilache
Differential Revision: https://reviews.llvm.org/D137264
2022-11-03 13:01:39 -04:00
Renaud-K
e2dd63340d Fixing flang's definition of MLIR_MAIN_SRC_DIR 2022-11-03 09:49:00 -07:00
Petar Avramovic
c060de72ec GlobalISel: Fix artifact combine value finder look through copy
Search for COPY source in instruction we get from look through (not copy dst).

Differential Revision: https://reviews.llvm.org/D137273
2022-11-03 17:43:25 +01:00
Peter Steinfeld
74d5c3c0f0 [Flang] Run clang-format on all flang files
This will make it easier for me to do reviews.

Differential Revision: https://reviews.llvm.org/D137291
2022-11-03 09:26:22 -07:00
Slava Zakharin
6f04011f15 [mlir][llvmir] Add support for llvm.signext/zeroext function attributes.
This change-set adds basic support for llvm.signext and llvm.zeroext
attributes, and makes sure that the attributes are translated to LLVM IR
when attached to arguments.

This is needed for https://github.com/llvm/llvm-project/issues/58579

Differential Revision: https://reviews.llvm.org/D137048
2022-11-03 09:19:02 -07:00
Michael Maitland
0eb2f663d2 [RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
It is likley that subtargets act differently for a vector integer arithmetic instruction based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL. It also
introduces the concept of an "UpperBound LMUL" which allows us to describe how an instruction should behave
when the LMUL is unknown. All base instructions use the UpperBound resources because they are not tied to
a specific LMUL. This gives subtargetes the flexibility to describe their own upper bounds on each vector
instruction.

I have a series of patches for the rest of the vector instruction set ready to go, but I would like to first
get feedback on the first one of the series (this one).

Differential Revision: https://reviews.llvm.org/D136730
2022-11-03 09:18:42 -07:00
David Green
e7deca5250 [AArch64] Alter arm_fp16.h to be target-based, not preprocessor based.
As the other recent patches, this alters the arm_fp16 intrinsics to be
target based, not preprocessor based. Apparently arm_fp16.h is AArch64
only under clang, making this mostly trivial with the TargetGuard
infrastructure.

Differential Revision: https://reviews.llvm.org/D137256
2022-11-03 16:06:35 +00:00
Slava Zakharin
473d001152 [mlir][llvmir] Convert attributes for functions without bodies.
So far the function argument attributes were only translated
for functions with bodies. This change makes sure that this
happens for functions without bodies (declarations) as well.

This is needed for https://github.com/llvm/llvm-project/issues/58579

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D137047
2022-11-03 08:52:19 -07:00
rkayaith
d97e8cd482 [mlir][python] Include anchor op in PassManager constructor
This adds an extra argument for specifying the pass manager's anchor op,
with a default of `any`. Previously the anchor was always defaulted to
`builtin.module`.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D136406
2022-11-03 11:52:16 -04:00
rkayaith
66645a03fc [mlir][python] Include anchor op in PassManager.parse
The pipeline string must now include the pass manager's anchor op. This
makes the parse API properly roundtrip the printed form of a pass
manager.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D136405
2022-11-03 11:49:48 -04:00
rkayaith
215eba4e1e [mlir][CAPI] Include anchor op in mlirParsePassPipeline
The pipeline string must now include the pass manager's anchor op. This
makes the parse API properly roundtrip the printed form of a pass
manager. Since this is already an API break, I also added an extra
callback argument which is used for reporting errors.

The old functionality of appending to an existing pass manager is
available through `mlirOpPassManagerAddPipeline`.

Reviewed By: mehdi_amini, ftynse

Differential Revision: https://reviews.llvm.org/D136403
2022-11-03 11:48:21 -04:00
rkayaith
d511a5d471 [mlir] Include anchor op in reproducer pipeline string
Including the anchor op ensures that all pass manager settings are fully
specified, and makes the string consistent with the printed form.

Depends on D134622

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D134623
2022-11-03 11:44:57 -04:00
Jan Sjodin
d7f0f4a0a2 [OpenMP][OMPIRBuilder] Migrate createOffloadEntriesAndInfoMetadata from clang to OpenMPIRBuilder
Remove unused [this] capture in lambda.
2022-11-03 11:41:21 -04:00
rkayaith
13bd410962 [mlir][Pass] Include anchor op in -pass-pipeline
In D134622 the printed form of a pass manager is changed to include the
name of the op that the pass manager is anchored on. This updates the
`-pass-pipeline` argument format to include the anchor op as well, so
that the printed form of a pipeline can be directly passed to
`-pass-pipeline`. In most cases this requires updating
`-pass-pipeline='pipeline'` to
`-pass-pipeline='builtin.module(pipeline)'`.

This also fixes an outdated assert that prevented running a
`PassManager` anchored on `'any'`.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D134900
2022-11-03 11:36:12 -04:00
Jay Foad
5073ae2a88 [AMDGPU] Fix duplicated words in comments 2022-11-03 15:33:30 +00:00
David Green
3edd188769 [AArch64] Add a baseline test for fp16 target intrinsics. NFC 2022-11-03 15:18:36 +00:00
LiDongjin
d1cee3539f [LoopVectorize] Fix crash on "Cannot dereference end iterator!"(PR56627)
Check hasOneUser before user_back().

Differential Revision: https://reviews.llvm.org/D136227
2022-11-03 23:13:37 +08:00
Nikita Popov
2ddcf721a0 [InstCombine] Perform memset -> load forwarding
InstCombine does some basic store to load forwarding. One case it
currently misses is the case where the store is actually a memset.
This patch adds support for this case. This is a minimal
implementation that only handles a load at the memset base address,
without an offset.

GVN is already capable of performing this optimization. Having it
in InstCombine can help with phase ordering issues, similar to the
existing store to load forwarding.

Differential Revision: https://reviews.llvm.org/D137323
2022-11-03 16:03:57 +01:00
Nikita Popov
d42cfc4be1 [SimplifyCFG] Add tests for block speculation with assumes (NFC) 2022-11-03 15:46:55 +01:00
zhijian
791411a037 [XCOFF] change the decoding of External symbol's function auxiliary entry in XCOFF32 for llvm-readobj
Summary:

llvm-readobj decide whether to decode the external symbol's function auxiliary entry based on whether symbol is function or not currently. But the XCOFFSymbolRef::isFunction() do not work properly when -ffunction-sections is enabled. we will not decode the function auxiliary entry based on the XCOFFSymbolRef::isFunction()
we will decode the function auxiliary entry based on following:
According to the https://www.ibm.com/docs/en/aix/7.2?topic=formats-xcoff-object-file-format#XCOFF__c0f91ad419jbau

In XCOFF32, there are only "one csect Auxiliary Entry" and "a function auxiliary symbol table entry" for the C_EXT, C_WEAKEXT, and C_HIDEXT Symbols. and By convention, the csect auxiliary entry in an XCOFF32 file must be the last auxiliary entry for any external symbol that has more than one auxiliary entry( that means for the C_EXT, C_WEAKEXT, and C_HIDEXT Symbols. if there more than one auxiliary Entries. we look the last one as csect auxiliary entry. and others auxiliary entries as function entries).

Reviewers: Hubert Tong, James Henderson
Differential Revision: https://reviews.llvm.org/D136950
2022-11-03 10:36:44 -04:00
Nikita Popov
68b24c3b44 [CVP] Simplify comparisons without constant operand
CVP currently only tries to simplify comparisons if there is a
constant operand. However, even if both are non-constant, we may
be able to determine the result of the comparison based on range
information.

IPSCCP is already capable of doing this, but because it runs very
early, it may miss some cases.

Differential Revision: https://reviews.llvm.org/D137253
2022-11-03 15:35:27 +01:00
bipmis
150fc73dda [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads
This patch is to address the test cases in which the load has to be inserted at a right point. This happens when there is a store b/w the loads.

This patch reverts the loads merge in all cases when stores are present b/w loads and will eventually be replaced with proper fix and test cases.

Differential Revision: https://reviews.llvm.org/D137333
2022-11-03 14:32:07 +00:00
Jan Sjodin
9ea2b150b5 [OpenMP][OMPIRBuilder] Migrate createOffloadEntriesAndInfoMetadata from clang to OpenMPIRBuilder
This patch moves the createOffloadEntriesAndInfoMetadata to OpenMPIRBuilder,
the createOffloadEntry helper function. The clang specific error handling is
invoked using a callback. This code will also be used by flang in the future.
2022-11-03 10:27:44 -04:00
Aaron Ballman
37f80101a9 Silence a "not all control paths return" MSVC warning; NFC 2022-11-03 10:27:16 -04:00
Nikita Popov
b03f7c3365 [SimplifyCFG] Use range based for loop (NFC) 2022-11-03 15:21:45 +01:00
Stefan Gränitz
dc9854d4e9 [JITLink] Fix check-line in Windows X86 COFF COMDAT test
This test caught my attention because it's the only one in JITLink that XFAILs. Running it in isolation showed that the output doesn't meet the CHECK-LINES, i.e. the block address didn't match:

```
error: CHECK-NEXT: expected string not found in input
  CHECK-NEXT: block 0xfff02000 size = 0x00000001, align = 16, alignment-offset = 0

<stdin>:22:2: note: possible intended match here
              block 0xfff01000 size = 0x00000001, align = 16, alignment-offset = 0
```

Though, that doesn't appear to be the reason the test XFAILs. What we really want to check here is that llvm-jitlink doesn't fail with a duplicate section error yet.
In order to avoid issues like this in the future we can match a placeholder to check for some valid address within the slab (64Kb == last 4 digits).

The patch also drops the duplicate -noexec argument, removes an empty RUN-line, fixes indentation and adds a newline at EOF.

Reviewed By: sunho

Differential Revision: https://reviews.llvm.org/D137148
2022-11-03 15:07:20 +01:00
OCHyams
fac26edae5 Revert "[Assignment Tracking][3/*] Add DIAssignID metadata boilerplate"
This reverts commit c285df77e9b78f971f9cd9d025248c20b030cc2a.

A sanitizer bot found an issue:
https://lab.llvm.org/buildbot/#/builders/5/builds/28809/steps/13/logs/stdio
2022-11-03 13:46:00 +00:00
Michael Buch
c188910694 [lldb][Test] Make TestFrameFormatNameWithArgs.test more compatible across platforms
On Linux the `std::function` behaved differently to that on Darwin.

This patch removes usage of `std::function` in the test but attempts
to retain the test-coverage. We mainly want function types appearing
in the template argument and function argument lists.

Also add a `char const*` overload to one of the test functions to
cover the "format function argument using ValueObject formatter" code-path.

Differential Revision: https://reviews.llvm.org/D137272
2022-11-03 06:30:14 -07:00
Stefan Pintilie
9df924a634 [PowerPC] Add new DMR register classes to Future CPU.
A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.

This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.

Reviewed By: amyk, saghir

Differential Revision: https://reviews.llvm.org/D136366
2022-11-03 08:29:55 -05:00
Nikita Popov
592a96c03b [SimplifyCFG] Extract code for tracking ephemeral values (NFC)
To allow reusing this in more places in SimplifyCFG.
2022-11-03 14:28:12 +01:00
Haojian Wu
964c4948cd Remove an unused local variable, NFC. 2022-11-03 13:57:46 +01:00
Alexey Bataev
f090e3c00f [SLP]Fix write after bounds.
Need to use comma instead of + symbol to prevent writing after bounds.
2022-11-03 05:30:41 -07:00
Alexey Bataev
8b015b2078 [SLP][NFC]Formatting and reduce number of iterations, NFC. 2022-11-03 05:30:13 -07:00
Aaron Ballman
b8ceb9f4e4 [C++20] Diagnose invalid and reserved module names
[module.unit]p1 specifies that module and import are invalid components
of a module name, that module names cannot contain reserved
identifiers, and that std followed by zero or more digits is reserved.

The first issue (module and import pseudo-keywords) requires a
diagnostic, the second issue (use of reserved identifiers) does not
require a diagnostic. We diagnose both the same -- the code is ill-
formed unless the module declaration is in a system "header". This
allows STL implementations to use the reserved module names while
preventing users from stealing them out from under us.

Differential Revision: https://reviews.llvm.org/D136953
2022-11-03 08:29:59 -04:00
bipmis
3ee1882299 Add another test which breaks the load insert point 2022-11-03 12:28:24 +00:00
Corentin Jabot
742970920b [Clang] Implement CWG2358 Explicit capture of value
Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D137172
2022-11-03 13:27:11 +01:00
Florian Hahn
44d8f80b26
[ConstraintElim] Use ConstantInt::getTrue to create constants (NFC).
Use existing ConstantInt::getTrue/getFalse functionality instead of
custom getScalarConstOrSplat as suggested by @nikic.
2022-11-03 12:20:23 +00:00
Mats Petersson
81181089c6 [Flang][Driver]Add datalayout before doing LLVM-IR transformation
The earlier available datalyaout allows MLIR to LLVM-IR transformation
to use the datalayout for decisions, such as comparing sizes for
different types of integers.

This should solve https://github.com/llvm/llvm-project/issues/57230

Reviewed By: awarzynski, vzakhari

Differential Revision: https://reviews.llvm.org/D133568
2022-11-03 12:16:22 +00:00
Yusuke Kadowaki
691774d403 [clang-format][NFC] Fix document of AlignTrailingComments
The documentation of the patch https://reviews.llvm.org/D132131 looks
disorganized on the website
https://clang.llvm.org/docs/ClangFormatStyleOptions.html.
This patch tries to fix that.

Differential Revision: https://reviews.llvm.org/D137075
2022-11-03 13:12:51 +01:00
Björn Schäpers
f97639ce13 [clang-format] Don't misannotate in CTor init list
They were annotated with TrailingAnnotation, which they are not. And
that resulted in some quirky formatting in some cases.

Differential Revision: https://reviews.llvm.org/D136635
2022-11-03 13:08:48 +01:00
Björn Schäpers
cdbe296853 [clang-format] Fix lambda formatting in conditional
Without the patch UnwrappedLineFormatter::analyzeSolutionSpace just ran
out of possible formattings and would put everything just on one line.
The problem was that the the line break was forbidden, but putting the
conditional colon on the same line is also forbidden.

Differential Revision: https://reviews.llvm.org/D135918
2022-11-03 13:08:14 +01:00
OCHyams
e53c4c6d86 [Assignment Tracking][3/*] Add DIAssignID metadata boilerplate
The Assignment Tracking debug-info feature is outlined in this RFC:

https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir

Add the DIAssignID metadata attachment boilerplate. Includes a textual-bitcode
roundtrip test and tests that the verifier and parser catch badly formed IR.

This piece of metadata links together stores (used as an attachment) and the
yet-to-be-added llvm.dbg.assign debug intrinsic (used as an operand).

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D132222
2022-11-03 11:24:18 +00:00
Valery Pykhtin
5144133f6f [AMDGPU] Fix GCNDownwardRPTracker::advanceBeforeNext at the end of MBB
The problem with GCNDownwardRPTracker::advanceBeforeNext is that it doesn't allow to get register pressure
after the last instruction in a MBB.

However when we track RP through the boundary of a MBB we need the state that is after the last instruction
of the MBB and before the first instruction of the successor MBB. Currently we stop traking RP in the state
 'at' the last instruction of the MBB which is incorrect.

This patch fixes 27 lit tests with EXPENSIVE_CHECKS enabled.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D136927
2022-11-03 11:52:56 +01:00
Tom Eccles
0fb763e7d0 [flang] Add -f[no-]honor-infinities and -menable-no-infs
Only add the option processing and store the result. No attributes are
added to FIR yet.

This patch follows Clang in forwarding -fno-honor-infinities as
-menable-no-infs.

Reviewed By: kiranchandramohan awarzynski vzakhari

Differential Revision: https://reviews.llvm.org/D137072
2022-11-03 10:38:09 +00:00
Nikita Popov
5945ab10c3 [InstCombine] Add more memset->load forwarding tests (NFC) 2022-11-03 10:56:32 +01:00