541806 Commits

Author SHA1 Message Date
David Green
8583882bdc [AArch64] Remove unnecessary DL variable. NFC 2025-06-22 10:52:13 +01:00
Mehdi Amini
075cb691a5
[MLIR] Add logging/tracing to DataFlow analysis and RemoveDeadValues (NFC) (#144695)
Debugging issues with this pass is quite difficult at the moment, this
should help.
2025-06-22 11:40:01 +02:00
Evan Liu
6ae5b89553
Make getStridesAndOffset const (#145148)
Make getStridesAndOffset const.
2025-06-22 11:21:47 +02:00
Florian Hahn
58b939abe5
[VPlan] Support matching constants in narrowInterleaveGroups.
Matching constants can trivially be broadcasted, allow them if the same
constant is used for all recipes in a bundle.
2025-06-22 08:45:40 +01:00
Abhishek Kaushik
cbfec48697
Revert "[X86][NFC] Use std::move to avoid copy" (#145215)
Reverts llvm/llvm-project#141455
2025-06-22 12:52:57 +05:30
Iris Shi
f51d8730b3
[InstSimplify] Simplify 'x u>= 1' to true when x is known non-zero (#145204) 2025-06-22 13:32:19 +08:00
Stanislav Mekhanoshin
fa0b84f23c
[AMDGPU] Rename call instructions from b64 to i64 (#145103)
These get renamed in gfx1250 and on from B64 to I64:

  S_CALL_I64
  S_GET_PC_I64
  S_RFE_I64
  S_SET_PC_I64
  S_SWAP_PC_I64
2025-06-21 21:42:09 -07:00
Craig Topper
b7d0c9b9d8
[SelectionDAG][RISCV] Treat zext nneg as sext in PromoteIntOp_ZERO_EXTEND if the promoted input is sign extended. (#145120)
If the zext has the nneg flag and we can prove the promoted input
is sign extended, we can avoid generating an AND that we might not
be able to remove. RISC-V emits a lot of sext_inreg operations during
i32->i64 promotion that makes this likely.

I've restricted this to the case where the promoted type is the same
as the result type so we don't need to create an additional extend.

I've also restricted it to cases where the target has stated a
preference for sext like i32->i64 on RV64. This is largely to avoid
wasting time in computeNumSignBits until we have a test case that
benefits.
2025-06-21 18:56:00 -07:00
Matt Arsenault
f280d3b705
AMDGPU: Avoid report_fatal_error for getRegisterByName subtarget case (#145173) 2025-06-22 08:19:19 +09:00
Arthur Eubanks
5708851283
Revert "[ValueTracking] Improve Bitcast handling to match SDAG" (#145191)
Reverts llvm/llvm-project#125935

Causes miscompiles, see comments in #125935
2025-06-21 16:02:26 -07:00
Douglas Yung
757c80d88a Add REQUIRES: x86 to test added in 141197 to skip when x86 target is not present. 2025-06-21 22:37:02 +00:00
Florian Hahn
c455f4a32d
[LV] Add more tests for narrowing interleave groups with live-ins. 2025-06-21 22:03:19 +01:00
eleviant
e066f35c69
[lldb] Fix qEcho message handling (#145072)
Patch fixes the sync-on-timeout logic in lldb and switches to qEcho
based ping, instead of qC. This fixes vRun message case, when there is
no process yet and qC returns an error.
2025-06-21 22:48:08 +02:00
Erick Velez
056b52df34
[clang-doc] Precommit test for global variables (#145069) 2025-06-21 11:56:35 -07:00
LLVM GN Syncbot
550ed9ef19 [gn build] Port e7dd223ec451 2025-06-21 18:10:42 +00:00
Katherine Whitlock
e7dd223ec4
[clang-tidy] Add new check readability-use-numeric-limits (#127430)
The adds a check that replaces specific numeric literals like `32767`
with the equivalent call to `std::numeric_limits` (such as
`std::numeric_limits<int16_t>::max())`.

Partially addresses #34434, but notably does not handle cases listed in
the title post such as `~0` and `-1`.
2025-06-21 21:10:20 +03:00
Tal Kedar
2ed089fb18
[clang/docs] add a missing brace in ClangFormatStyleOptions.rst (#145145)
... in the example for `WrapNamespaceBodyWithEmptyLines: Never`
2025-06-21 20:00:22 +02:00
Mikhail R. Gadelha
6c8c816b17
[libc] Fix feature check for riscv (#145169)
This PR fixes the feature detection for RISC-V floating-point support in
LLVM's libc implementation.

The `__riscv_flen` macro represents the floating-point register width in
bits (32, 64, or 128). Since Extension D is specifically documented as
implying F, we can use simple >= comparisons to detect them.

For half-precision support, the implementation checks for the Zfhmin
extension as RVA22 and RVA23 profiles only require Zfhmin rather than
the full Zfh extension. Zfh also implies Zfhmin, so checking for Zfhmin
should cover all cases.
2025-06-21 14:42:45 -03:00
Craig Topper
0c47628515 Re-commit "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)"
With proper co-author.

Original message:

We need to pass the operand of LLA to GetSupportedConstantPool.

This replaces #142292 with test from there added as a pre-commit
for both medlow and pic.

Co-authored-by: Carl Nettelblad carl.nettelblad@rapidity-space.com
2025-06-21 10:18:49 -07:00
Craig Topper
fc36e47a49 Revert "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)"
I missed the Co-authored-by that I tried to add.

This reverts commit 1da864b574f699d5c9be68dca9b3969ad50f4803.
2025-06-21 10:18:34 -07:00
Craig Topper
1da864b574
[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)
We need to pass the operand of LLA to GetSupportedConstantPool.
    
This replaces #142292 with test from there added as a pre-commit
for both medlow and pic.
2025-06-21 10:17:30 -07:00
Florian Hahn
9f7a155394
[VPlan] Update packScalarIntoVector to take and return wide value (NFC)
Make the function more flexible in preparation for new users.
2025-06-21 18:03:14 +01:00
Abhishek Kaushik
4c1a1009ad
[X86][NFC] Use std::move to avoid copy (#141455) 2025-06-21 22:04:41 +05:30
Kazu Hirata
463ce01310
[CodeGen] Remove extraneous casts to VariableID (NFC) (#145144)
We do not need these casts because values being cast here are already
of type VariableID.
2025-06-21 08:21:04 -07:00
Kazu Hirata
ae372bfca8
[CodeGen] Use range-based for loops (NFC) (#145142) 2025-06-21 08:20:57 -07:00
Kazu Hirata
e6ebf8f99b
[mlir] Migrate away from ArrayRef(std::nullopt) (NFC) (#145140)
ArrayRef has a constructor that accepts std::nullopt.  This
constructor dates back to the days when we still had llvm::Optional.

Since the use of std::nullopt outside the context of std::optional is
kind of abuse and not intuitive to new comers, I would like to move
away from the constructor and eventually remove it.

This patch takes care of the mlir side of the migration, starting with
straightforward places like "return std::nullopt;" and ternally
expressions involving std::nullopt.
2025-06-21 08:20:49 -07:00
Kunqiu Chen
99af99c665
[TSan] Fix p == end == ShadowMem::end in ShadowSet (#144994)
In `ShadowSet`, when `p == end == ShadowMem::end`, it triggered an
assertion fail previously.

Now we do not allow `p == end` anymore in `ShadowSet`.
2025-06-21 23:02:41 +08:00
Matt Arsenault
a961ba88e1
AMDGPU: Use reportFatalUsageError for LDS mixed absolute addresses (#145135) 2025-06-21 23:54:27 +09:00
Florian Hahn
60d1276b0e
[VPlan] Pass operand index to canNarrowLoad. (NFC)
Explicitly pass the operand we are checking to canNarrowLoad. This
simplifies the check if the operands match across recipes and enables
future optimizations.
2025-06-21 15:41:26 +01:00
Hui
831fcb5e91
[libc++] constexpr flat_map (#137453)
Fixes #128673
2025-06-21 13:41:32 +01:00
David Green
77941eba7f
[CostModel] Add a DstTy to getShuffleCost (#141634)
A shuffle will take two input vectors and a mask, to produce a new
vector of size <MaskElts x SrcEltTy>. Historically it has been assumed
that the SrcTy and the DstTy are the same for getShuffleCost, with that
being relaxed in recent years. If the Tp passed to getShuffleCost is the
SrcTy, then the DstTy can be calculated from the Mask elts and the src
elt size, but the Mask is not always provided and the Tp is not reliably
always the SrcTy. This has led to situations notably in the SLP
vectorizer but also in the generic cost routines where assumption about
how vectors will be legalized are built into the generic cost routines -
for example whether they will widen or promote, with the cost modelling
assuming they will widen but the default lowering to promote for integer
vectors.

This patch attempts to start improving that - it originally tried to
alter more of the cost model but that too quickly became too many
changes at once, so this patch just plumbs in a DstTy to getShuffleCost
so that DstTy and SrcTy can be reliably distinguished. The callers of
getShuffleCost have been updated to try and include a DstTy that is more
accurate. Otherwise it tries to be fairly non-functional, keeping the
SrcTy used as the primary type used in shuffle cost routines, only using
DstTy where it was in the past (for InsertSubVector for example).

Some asserts have been added that help to check for consistent values
when a Mask and a DstTy are provided to getShuffleCost. Some of them
took a while to get right, and some non-mask calls might still be
incorrect. Hopefully this will provide a useful base to build more
shuffles that alter size.
2025-06-21 12:29:29 +01:00
yronglin
ea321392eb
[C++][Modules] A module directive may only appear as the first preprocessing tokens in a file (#144233)
This PR is 2nd part of
[P1857R3](https://github.com/llvm/llvm-project/pull/107168)
implementation, and mainly implement the restriction `A module directive
may only appear as the first preprocessing tokens in a file (excluding
the global module fragment.)`:
[cpp.pre](https://eel.is/c++draft/cpp.pre):
```
module-file:
    pp-global-module-fragment[opt] pp-module group[opt] pp-private-module-fragment[opt]
```

We also refine tests use `split-file` instead of conditional macro.

Signed-off-by: yronglin <yronglin777@gmail.com>
2025-06-21 18:58:56 +08:00
Baranov Victor
1b5d6ec685
[clang-tidy] count class member initializers as statements in 'readability-function-size' (#131669)
Improve `readability-function-size` by counting class member
initializers as statements.
Relates to https://github.com/llvm/llvm-project/issues/131126
2025-06-21 13:14:19 +03:00
LLVM GN Syncbot
369e8403b6 [gn build] Port 1bb2328fd3ad 2025-06-21 09:55:19 +00:00
Jakub Mazurkiewicz
1bb2328fd3
[libc++] Implement views::join_with (#65536)
* Implement "P2441R2 `views::join_with`" (https://wg21.link/P2441R2),
closes #105185
* Implement LWG4074 (https://wg21.link/LWG4074), closes #105346
* Complete implementation of "P2711R1 Making multi-param constructors of
views explicit" (https://wg21.link/P2711R1), closes #105252
* Complete implementation of "P2770R0 Stashing stashing iterators for
proper flattening" (https://wg21.link/P2770R0), closes #105250
2025-06-21 10:54:50 +01:00
Lang Hames
d6a486c221
[ORC] Apply MachO::CPU_SUBTYPE_MASK to comparison in getDylibInterfac… (#145154)
…eFromDylib.

When comparing CPU subtypes from slices in a MachO universal binary we
need to apply the MachO::CPU_SUBTYPE_MASK to mask out any flags in the
high bits, otherwise we might fail to correctly match a slice and return
a spurious "does not contain slice" error.

rdar://153913779
2025-06-21 19:31:51 +10:00
Florian Hahn
2f5d965bb5
[VPlan] Use EMIT-SCALAR when printing casts.
Split off EMIT-SCALAR printing changes from already approved
https://github.com/llvm/llvm-project/pull/140623.

Currently all casts are single scalars, this brings printing in line
with printing for other VPInstructions.
2025-06-21 10:23:53 +01:00
Michele Scuttari
bb372963df
[MLIR] Add optional cached symbol tables to LLVM conversion patterns (#144032)
This PR allows to optionally speed up the lookup of symbols by providing a `SymbolTableCollection` instance to the interested conversion patterns. It is follow-up on the discussion about symbol / symbol table management carried on [Discourse](https://discourse.llvm.org/t/symbol-table-as-first-class-citizen-in-builders/86813).
2025-06-21 10:55:44 +02:00
Matthias Springer
0921bfd81d
[mlir][Transforms] Dialect conversion: Add missing erasure notifications (#145030)
Add missing listener notifications when erasing nested
blocks/operations.

This commit also moves some of the functionality from
`ConversionPatternRewriter` to `ConversionPatternRewriterImpl`. This is
in preparation of the One-Shot Dialect Conversion refactoring: The
implementations in `ConversionPatternRewriter` should be as simple as
possible, so that a switch between "rollback allowed" and "rollback not
allowed" can be inserted at that level. (In the latter case,
`ConversionPatternRewriterImpl` can be bypassed to some degree, and
`PatternRewriter::eraseBlock` etc. can be used.)

Depends on #145018.
2025-06-21 10:44:54 +02:00
Amr Hesham
4a4582dd78
[CIR] Upstream BinAssign for ComplexType (#144868)
This change adds support for the BinAssign op and LValueToRValue for
ComplexType

https://github.com/llvm/llvm-project/issues/141365
2025-06-21 10:30:59 +02:00
Matt Arsenault
5f2135df17
AMDGPU: Really delete AMDGPUAnnotateKernelFeatures (#145136) 2025-06-21 17:25:30 +09:00
Corentin Jabot
c69f97cb95 [Clang] Add WG21 papers from the Sofia meeting to the status page 2025-06-21 11:17:19 +03:00
Nikolas Klauser
685af55fe0
[libc++] Simplify <limits> a bit (#140021)
This does a few small things:
- inline `__libcpp_compute_min`, since we can don't have to put the
arithmetic behind a constraint. Simple arithmetic also tends to be
faster to compile than instantiating a type.
- Remove an unused include (and add missing includes elsewhere)
- Remove `__min` and `__max` from the `bool` specialization

Co-authored-by: Louis Dionne <ldionne.2@gmail.com>
2025-06-21 09:58:45 +02:00
Nikolas Klauser
2050d2e181
[libc++] Simplify std::function further after removing allocator support (#144443)
Since we've removed allocator support, we can remove a few support
structures. This only affects the policy implementation, so this
shouldn't even be ABI sensitive.
2025-06-21 09:47:54 +02:00
Matthias Springer
32dbaf12be
[mlir][Transforms][NFC] Dialect conversion: Rename internal functions (#145018)
Rename a few internal functions: drop the `notify` prefix, which
incorrectly suggests that the function is a listener callback function.
2025-06-21 09:43:34 +02:00
David Green
437346378f
[GlobalISel] Widen vector loads from aligned ptrs (#144309)
If the pointer is aligned to more than the size of the vector, we can
widen the load up to next power of 2 size, as SDAG performs.

Some of the v3 tests are currently worse - those should be addressed in
other issues.
2025-06-21 07:42:54 +01:00
David Green
1fec092fd7
[AArch64][GlobalISel] Allow selecting FPR index loads. (#143835)
We can, through legalization of certain operations, end up generating
G_INDEXED_LOAD into FPR registers that require entensions. SExt and ZExt
will always opt for GPR, but anyext/noext can curently be set to FPR
registers in regbankselect. As writing a subregister will set higher
bits in the same register to 0, we can successfully handle zext and
anyext on FPR registers, which is what this patch attempts to add.
2025-06-21 07:01:35 +01:00
Sam Elliott
cb4f329004
[RISCV] Fix HasStdExtCOrZcfOrZce Syntax (#145141) 2025-06-20 22:44:55 -07:00
Haohai Wen
9cc9efc483
[lld][COFF] Remove duplicate strtab entries (#141197)
String table size is too big for large binary when symbol table is
enabled. Some strings in strtab is same so it can be reused.

This patch revives 9ffeaaa authored by mstorsjo with the prioritized
string table builder to fix debug section name issue (see 4d2eda2
for more details).

---------

Co-authored-by: Wen Haohai <whh108@live.com>
Co-authored-by: James Henderson <James.Henderson@sony.com>
2025-06-21 13:44:10 +08:00
Matt Arsenault
0fa0c3c233
AMDGPU: Use reportFatalUsageError in AMDGPULowerBufferFatPointers (#145132) 2025-06-21 14:24:30 +09:00