402 Commits

Author SHA1 Message Date
Matt Arsenault
9383fb23e1
Reapply "IR: Remove uselist for constantdata (#137313)" (#138961)
Reapply "IR: Remove uselist for constantdata (#137313)"

This reverts commit 5936c02c8b9c6d1476f7830517781ce8b6e26e75.

Fix checking uselists of constants in assume bundle queries
2025-05-08 08:00:09 +02:00
Kirill Stoimenov
5936c02c8b Revert "IR: Remove uselist for constantdata (#137313)"
Possibly breaks the build: https://lab.llvm.org/buildbot/#/builders/24/builds/8119

This reverts commit 87f312aad6ede636cd2de5d18f3058bf2caf5651.
2025-05-07 00:07:55 +00:00
Matt Arsenault
87f312aad6
IR: Remove uselist for constantdata (#137313)
This is a resurrected version of the patch attached to this RFC:

https://discourse.llvm.org/t/rfc-constantdata-should-not-have-use-lists/42606

In this adaptation, there are a few differences. In the original patch, the Use's
use list was replaced with an unsigned* to the reference count in the value. This
version leaves them as null and leaves the ref counting only in Value.

Remove use-lists from instances of ConstantData (which are shared
across modules and have no operands).

To continue supporting most of the use-list API, store a ref-count in
place of the use-list; this is for API like Value::use_empty and
Value::hasNUses.  Operations that actually need the use-list -- like
Value::use_begin -- will assert.

This change has three benefits:

 1. The compiler output cannot in any way depend on the use-list order
    of instances of ConstantData.

 2. There's no use-list traffic when adding and removing simple
    constants from operand lists (although there is ref-count traffic;
    YMMV).

 3. It's cheaper to serialize use-lists (since we're no longer
    serializing the use-list order of things like i32 0).

The downside is that you can't look at all the users of ConstantData,
but traversals of users of i32 0 are already ill-advised.

Possible follow-ups:
  - Track if an instance of a ConstantVector/ConstantArray/etc. is known
    to have all ConstantData arguments, and drop the use-lists to
    ref-counts in those cases.  Callers need to check Value::hasUseList
    before iterating through the use-list.
  - Remove even the ref-counts.  I'm not sure they have any benefit
    besides minimizing the scope of this commit, and maintaining the
    counts is not free.

Fixes #58629

Co-authored-by: Duncan P. N. Exon Smith <dexonsmith@apple.com>
2025-05-06 17:20:37 +02:00
Yingwei Zheng
1f69d6354a
[InstCombine] Preserve the sign bit of NaN in SimplifyDemandedUseFPClass (#137287)
Alive2: https://alive2.llvm.org/ce/z/uiUzEf

Closes https://github.com/llvm/llvm-project/issues/137196.

Note: To avoid regression in
`ret_nofpclass_nopositives_copysign_nnan_flag`, the second commit takes
FMF into account.
2025-04-28 17:01:43 +08:00
Fangrui Song
2131115be5
[InstCombine] Drop Range attribute when simplifying 'fshl' based on demanded bits (#124429)
When simplifying operands based on demanded bits, the return value range
of llvm.fshl might change. Keeping the Range attribute might cause
llvm.fshl to generate a poison and lead to miscompile. Drop the Range
attribute similar to `dropPosonGeneratingFlags` elsewhere.

Fix #124387
2025-01-25 13:35:11 -08:00
Yingwei Zheng
295d6b18f7
[InstCombine] Fold (X * (Y << K)) u>> K -> X * Y when highbits are not demanded (#111151)
Alive2: https://alive2.llvm.org/ce/z/Z7QgjH
2024-12-03 12:04:04 +08:00
Yingwei Zheng
03d8831fa8
[InstCombine] Handle constant GEP expr in SimplifyDemandedUseBits (#116794)
Closes https://github.com/llvm/llvm-project/issues/116775.
2024-11-19 22:17:24 +08:00
Princeton Ferro
10f35a04c9
[InstCombine] add control for SimplifyDemandedVectorElts depth limit (#113717)
Allows customizing the depth of the recursive search on vectors that
InstCombine does when looking for unused elements.

We find it helpful to be able to customize this for compile time
reasons.
2024-11-09 10:54:39 +01:00
Rahul Joshi
fa789dffb1
[NFC] Rename Intrinsic::getDeclaration to getOrInsertDeclaration (#111752)
Rename the function to reflect its correct behavior and to be consistent
with `Module::getOrInsertFunction`. This is also in preparation of
adding a new `Intrinsic::getDeclaration` that will have behavior similar
to `Module::getFunction` (i.e, just lookup, no creation).
2024-10-11 05:26:03 -07:00
Benjamin Maxwell
6b3220afa6
[InstCombine] Avoid crash on aggregate types in SimplifyDemandedUseFPClass (#111128)
The disables folding for FP aggregates that are not poison/posZero
types, which is currently not supported. Note: To fully handle this
aggregates would also likely require teaching `computeKnownFPClass()` to
handle array and struct constants (which does not seem implemented
outside of zero init).
2024-10-04 15:00:24 +01:00
Yingwei Zheng
62cd07fb67
[InstCombine] Canonicalize sub mask, X -> ~X when high bits are ignored (#110635)
Alive2: https://alive2.llvm.org/ce/z/NJgBPL

The motivating case of this patch is to emit `andn` on RISC-V with zbb
for expressions like `(sub 63, X) & 63`.
2024-10-02 12:48:06 +08:00
Nikita Popov
e2a855def5 [InstCombine] Fix SimplifyDemandedBits recursion cutoff for Arguments
There was a discrepancy between how SimplifyDemandedBits and
computeKnownBits handled the Argument case. computeKnownBits()
would use information from range attributes even once the
recursion limit has been reached.

Fixes https://github.com/llvm/llvm-project/issues/110631.
2024-10-01 11:44:13 +02:00
Ramkumar Ramachandra
1832d609f7
InstCombine/Demanded: simplify srem case (NFC) (#110260)
The srem case of SimplifyDemandedUseBits partially duplicates
KnownBits::srem. It is guarded by a statement that takes the absolute
value of the RHS and checks whether it is a power of 2, but the abs()
call here useless, since an srem with a negative RHS is flipped into one
with a positive RHS, adjusting LHS appropriately. Stripping the abs call
allows us to call KnownBits::srem instead of partially duplicating it.
2024-09-27 19:12:35 +01:00
Nikita Popov
5ef02a3fd4 [InstCombine] Fall through to computeKnownBits() for sdiv by -1
When dividing by -1 we were breaking out of the code entirely,
while we should fall through to computeKnownBits().

This fixes an instcombine-verify-known-bits discrepancy.

Fixes https://github.com/llvm/llvm-project/issues/109957.
2024-09-25 14:23:06 +02:00
Simon Pilgrim
11ba72e651
[KnownBits] Add KnownBits::add and KnownBits::sub helper wrappers. (#99468) 2024-08-12 10:21:28 +01:00
Jorge Botto
9304af3927
[InstCombine] Fixing wrong select folding in vectors with undef elements (#102244)
This PR fixes https://github.com/llvm/llvm-project/issues/98435.
`SimplifyDemandedVectorElts` mishandles the undef by assuming that
!isNullValue() means the condition is true.

By preventing any value that we're not certain equals 1 or 0, it avoids
having to make any particular choice by not demanding bits from a
particular branch with potentially picking a wrong value.

Proof: https://alive2.llvm.org/ce/z/r8CmEu
2024-08-09 12:52:56 +02:00
Yingwei Zheng
62e9f40949
[PatternMatch] Use m_SpecificCmp matchers. NFC. (#100878)
Compile-time improvement:
http://llvm-compile-time-tracker.com/compare.php?from=13996378d81c8fa9a364aeaafd7382abbc1db83a&to=861ffa4ec5f7bde5a194a7715593a1b5359eb581&stat=instructions:u
baseline: 803eaf29267c6aae9162d1a83a4a2ae508b440d3
```
Top 5 improvements:
  stockfish/movegen.ll 2541620819 2538599412 -0.12%
  minetest/profiler.cpp.ll 431724935 431246500 -0.11%
  abc/luckySwap.c.ll 581173720 580581935 -0.10%
  abc/kitTruth.c.ll 2521936288 2519445570 -0.10%
  abc/extraUtilTruth.c.ll 1216674614 1215495502 -0.10%
Top 5 regressions:
  openssl/libcrypto-shlib-sm4.ll 1155054721 1155943201 +0.08%
  openssl/libcrypto-lib-sm4.ll 1155054838 1155943063 +0.08%
  spike/vsm4r_vv.ll 1296430080 1297039258 +0.05%
  spike/vsm4r_vs.ll 1312496906 1313093460 +0.05%
  nuttx/lib_rand48.c.ll 126201233 126246692 +0.04%
Overall: -0.02112308%
```
2024-07-29 10:04:06 +08:00
Bjorn Pettersson
b8c4c58ecf [InstCombine] Turn AShr into LShr more often in SimplifyDemandedUseBits (#99155)
The functional change here is to undo "llvm-svn: 311773", aka D36936,
aka commit 22178dd33b3460207b8. That patch avoided to convert AShr
into LShr in SimplifyDemandedUseBits based on known sign bits
analysis. Even if it would be legal to turn the shift into a
logical shift (given by the fact that the shifted in bits wasn't
demanded), that patch prevented converting the shift into LShr when
any of the original sign bits were demanded.
One side effect of the reverted functionalty was that the better we
were at computing number of sign bits, the less likely it was that
we would replace AShr by LShr during SimplifyDemandedUseBits. This
was seen in https://github.com/llvm/llvm-project/pull/97693/ when
an improvement of ComputeNumSignBits resulted in regressions due
to no longer rewriting AShr to LShr.
The test case from D36936 still passes after this commit. So it seems
like at least the compiler has been taught how to optimize that
scenario even if we do the AShr->LShr transform more aggressively.
2024-07-18 11:25:43 +02:00
Yingwei Zheng
722151664e
[InstCombine] Fix typo in adjustKnownBitsForSelectArm (#98155)
Fixes https://github.com/llvm/llvm-project/issues/98139.
2024-07-09 22:04:55 +08:00
Nikita Popov
05670b42f5 [InstCombine] Remove root special case in demanded bits simplification
When calling SimplifyDemandedBits (as opposed to
SimplifyDemandedInstructionBits), and there are multiple uses,
always use SimplifyMultipleUseDemandedBits and drop the special
case for root values.

This fixes the ephemeral value detection, as seen by the restored
assumes in tests. It may result in more or less simplification,
depending on whether we get more out of having demanded bits or
the ability to perform non-multi-use transforms. The change in
the phi-known-bits.ll test is because the icmp operand now gets
simplified based on demanded bits, which then prevents a different
known bits simplification later.

This also makes the code safe against future changes like
https://github.com/llvm/llvm-project/pull/97289, which add more
context that would have to be discarded for the multi-use case.
2024-07-02 11:14:36 +02:00
Nikita Popov
86b37944a7 Reapply [InstCombine] Fix context for multi-use demanded bits simplification
Repplied with a clang test fix.

-----

When simplifying a multi-use root value, the demanded bits were
reset to full, but we also need to reset the context instruction.
To make this convenient (without requiring by-value passing of
SimplifyQuery), move the logic that handles constants and
dispatches to SimplifyDemandedUseBits/SimplifyMultipleUseDemandedBits
into SimplifyDemandedBits. The SimplifyDemandedInstructionBits
caller starts with full demanded bits and an appropriate context
anyway.

The different context instruction does mean that the ephemeral
value protection no longer triggers in some cases, as the changes
to assume tests show.

An alternative, which I will explore in a followup, is to always
use SimplifyMultipleUseDemandedBits() -- the previous root special
case is only really intended for SimplifyDemandedInstructionBits(),
which now no longer shares this code path.

Fixes https://github.com/llvm/llvm-project/issues/97330.
2024-07-02 11:02:55 +02:00
Nikita Popov
167c860ba2 Revert "[InstCombine] Fix context for multi-use demanded bits simplification"
This reverts commit b558ac0eef57a3737b1e27844115fa91e0b32582.

This breaks a clang test, reverting for now.
2024-07-02 10:44:34 +02:00
Nikita Popov
b558ac0eef [InstCombine] Fix context for multi-use demanded bits simplification
When simplifying a multi-use root value, the demanded bits were
reset to full, but we also need to reset the context extract. To
make this convenient (without requiring by-value passing of
SimplifyQuery), move the logic that that handles constants and
dispatches to SimplifyDemandedUseBits/SimplifyMultipleUseDemandedBits
into SimplifyDemandedBits. The SimplifyDemandedInstructionBits
caller starts with full demanded bits and an appropriate context
anyway.

The different context instruction does mean that the ephemeral
value protection no longer triggers in some cases, as the changes
to assume tests show.

An alternative, which I will explore in a followup, is to always
use SimplifyMultipleUseDemandedBits() -- the previous root special
case is only really intended for SimplifyDemandedInstructionBits(),
which now no longer shares this code path.

Fixes https://github.com/llvm/llvm-project/issues/97330.
2024-07-02 10:32:27 +02:00
Nikita Popov
b58ae6bd27 [InstCombine] Sync KnownBits logic for select arms
Extract an adjustKnownBitsForSelectArm() helper for the
ValueTracking logic and make use of it in SimplifyDemandedBits().

This fixes a consistency violation under instcombine-verify-known-bits.
2024-07-01 15:52:20 +02:00
Nikita Popov
154c8a02ed [InstCombine] Use KnownBits::ashr()
This fixes a consistency violation under -instcombine-verify-known-bits.
2024-07-01 14:52:06 +02:00
Nikita Popov
11484cb817 [InstCombine] Pass SimplifyQuery to SimplifyDemandedBits()
This will enable calling SimplifyDemandedBits() with a SimplifyQuery
that has CondContext set in the future.

Additionally this also marginally strengthens the analysis by
retaining the original context instruction for one-use chains.
2024-07-01 12:41:21 +02:00
AtariDreams
dd0245e3d7
[InstCombine] Relax one-use requirement for add iN (sext i1 X), (sext i1 Y) --> sext (X | Y) to iN (#90509)
Since these remove instructions as long as at least one of X or Y is
one-use, we don't need to check one-use for both.
2024-06-28 09:08:01 +02:00
Nikita Popov
79e668f970 [InstCombine] Fix funnel shift bailout in demanded bits simplification
We shouldn't simply return here -- we still need to compute the
known bits and fall through to generic handling.

This fixes a -instcombine-verify-known-bits violation in funnel.ll.
2024-06-18 14:39:06 +02:00
Nikita Popov
ced41a125c [InstCombine] Remove redundant urem demanded bits case
This does the recursive simplification with all bits demanded,
which is not useful. Fall through to the fallback case instead.
2024-06-18 14:16:03 +02:00
c8ef
b25b1db819
[KnownBits] Remove hasConflict() assertions (#94568)
Allow KnownBits to represent "always poison" values via conflict.

close: #94436
2024-06-07 17:01:22 +02:00
hanbeom
44c79da3ae
[InstCombine] Remove shl if we only demand known signbits of shift source (#79014)
This patch resolve TODO written in commit:
5909c67883

Proof: https://alive2.llvm.org/ce/z/C3VNoR
2024-04-10 11:19:09 +09:00
Jon Chesterfield
6157538d9e
[InstCombine] ptrmask of gep for dynamic pointer aligment (#80002)
Targets the dynamic realignment pattern of `(Ptr + Align - 1) & -Align;`
as implemented by gep then ptrmask.

Specifically, when the pointer already has alignment information,
dynamically realigning it to less than is already known should be a
no-op. Discovered while writing test cases for another patch.

For the zero low bits of a known aligned pointer, adding the gep index
then removing it with a mask is a no-op. Folding the ptrmask effect
entirely into the gep is the ideal result as that unblocks other
optimisations that are not aware of ptrmask.

In some other cases the gep is known to be dead and is removed without
changing the ptrmask.

In the least effective case, this transform creates a new gep with a
rounded-down index and still leaves the ptrmask unchanged. That
simplified gep is still a minor improvement, geps are cheap and ptrmask
occurs in address calculation contexts so I don't think it's worth
special casing to avoid the extra instruction.
2024-03-07 17:36:28 +00:00
Noah Goldstein
61c06775c9 [KnownBits] Add API for nuw flag in computeForAddSub; NFC 2024-03-05 12:59:58 -06:00
Antonio Frighetto
d2a26a7bd5 [InstCombine] Do not perform binop-of-shuffle when mask is poison
A miscompilation issue has been addressed with refined checking.
Shuffle masks operand may be turned into `poison` if this does
not lead to observable changes. This however may not guarantee
binop to binop-of-shuffle replacement to be sound anymore.

Fixes: https://github.com/llvm/llvm-project/issues/82052.
2024-02-20 08:37:51 +01:00
Eikansh Gupta
3363d23bd3 [InstCombine] Do not simplify lshr/shl arg if it is part of a rotate pattern
fshl/fshr having first two arguments as same gets lowered to target
specific rotate. But based on the uses, one of the arguments can get
simplified resulting in different arguments performing equivalent
operation.

This patch prevents the simplification of the arguments of lshr/shl if
they are part of fshl pattern.

Closes https://github.com/llvm/llvm-project/pull/73441.
2024-02-16 16:52:00 +01:00
Matt Arsenault
decbd29f9e
Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (#74056)
This reverts commit ef388334ee5a3584255b9ef5b3fefdb244fa3fd7.

The referenced issue violates the spec for finite-only math only by
using a return value for a constant infinity. If the interpretation
is results and arguments cannot violate nofpclass, then any
std::numeric_limits<T>::infinity() result is invalid under
-ffinite-math-only. Without this interpretation the utility of
nofpclass is slashed.
2024-02-08 14:12:39 +05:30
Yingwei Zheng
cb8d83a77c
[InstCombine] Fix assertion failure in issue80597 (#80614)
The assertion in #80597 failed when we were trying to compute known bits
of a value in an unreachable BB.

859b09da08/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (L749-L810)

In this case, `SignBits` is 30 (deduced from instr info), but `Known` is
`10000101010111010011110101000?0?00000000000000000000000000000000`
(deduced from dom cond). Setting high bits of `lshr Known, 1` will lead
to conflict.

This patch masks out high bits of `Known.Zero` to address this problem.

Fixes #80597.
2024-02-06 01:29:38 +08:00
Nikita Popov
f412b78ffc [InstCombine] Return poison if all lanes are poison 2023-12-19 12:43:23 +01:00
Nikita Popov
9d4557920f [InstCombine] Don't treat undef as poison in demanded element simplification
We can only set PoisonElts if the element is poison, not if it is
undef.
2023-12-19 12:26:48 +01:00
Nikita Popov
e400c59beb Revert "[InstCombine] Favour m_Poison in SimplifyDemandedVectorElts"
This reverts commit 318d5bff0b65aa7d52fc7004d49587416f0fb564.

Has incomplete test updates.
2023-12-18 18:08:57 +01:00
Antonio Frighetto
318d5bff0b [InstCombine] Favour m_Poison in SimplifyDemandedVectorElts
A miscompilation issue has been addressed with refined checking.
2023-12-18 17:28:39 +01:00
Nikita Popov
a5f3415533 [InstCombine] Replace non-demanded undef vector with poison
If an operand (esp to shufflevector or insertelement) is not
demanded, canonicalize it from undef to poison.
2023-12-18 16:12:37 +01:00
Nikita Popov
d0605e21af [InstCombine] Canonicalize splat shuffles to use poison operand
If the splat shuffle is represented using an undef RHS, replace it
with poison.
2023-12-18 15:57:49 +01:00
Nikita Popov
465ecf872e [InstCombine] Rename UndefElts -> PoisonElts (NFC)
In line with updated shufflevector semantics, this represents the
poison elements rather than undef elements now. This commit is a
pure rename, without any logic changes.
2023-12-18 12:36:19 +01:00
Antonio Frighetto
151ddf07a6 [InstCombine] Stop propagating undef when element is demanded
Do not poison `undef` demanded elements in `SimplifyDemandedVectorElts`.
A miscompilation issue has been addressed with refined checking.

Proofs: https://alive2.llvm.org/ce/z/WA5oD5.
2023-12-17 21:41:03 +01:00
Nikita Popov
9100228e45 [InstCombine] Fix insertion point 2023-12-14 15:27:17 +01:00
Fujun Han
7be5dabbc2
[InstCombine] Change (add x, c) to (xor x, c) (#75129)
Change (add x, c) to (xor x, c) iff c is constant and c equals the top bit of the demanded bits.
Alive2: https://alive2.llvm.org/ce/z/DKmkwF

---------

Signed-off-by: Peter Han <fujun.han@iluvatar.com>
Co-authored-by: Peter Han <fujun.han@iluvatar.com>
2023-12-14 21:19:15 +08:00
Craig Topper
56248caa3b
[InstCombine] Explicitly set disjoint flag when converting xor to or. (#74229) 2023-12-06 09:41:59 -08:00
Craig Topper
76cd0355cb [InstCombine] Preserve exact instruction name for xor->or transform in SimplifyDemandedUseBits.
We were previously retaining the name with a numeric suffix.
2023-12-02 23:21:59 -08:00
Craig Topper
bdcf2087d9 Recommit "[InstCombine] Retain exact instruction name for some cases in SimplifyDemandedUseBits."
It looks like my original patch got caught up in
ef388334ee5a3584255b9ef5b3fefdb244fa3fd7 that was reverting a different
patch.

Original message:
Retain name for SExt->ZExt and AShr->LShr. Previously SExt->ZExt copied
the name with a numeric suffix. AShr->LShr dropped it.
2023-12-02 20:53:34 -08:00