10211 Commits

Author SHA1 Message Date
Sameer Sahasrabuddhe
d9847cde48 [GlobalISel] convergent intrinsics
Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets that currently have some support for GlobalISel, the patch
assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154766
2023-07-31 12:15:39 +05:30
Cyndy Ishida
20c92d26d9 [docs] Add links to recent transparency reports
Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D156456
2023-07-28 07:40:48 -07:00
melonedo
afb9c04a5a [RISCV] Add support for XCVbi extension in CV32E40P
Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj.

bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited.
e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in.
This commit removed the conflict marker and recommitted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412
2023-07-28 21:54:10 +08:00
melonedo
e4777dc4b9 Revert "[RISCV] Add support for XCVbi extension in CV32E40P"
This reverts commit bf2ad26b4ff856aab9a62ad168e6bdefeedc374f as it
checked in merge conflict markers.
2023-07-28 19:28:20 +08:00
melonedo
bf2ad26b4f [RISCV] Add support for XCVbi extension in CV32E40P
Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412
2023-07-28 17:36:57 +08:00
melonedo
3c0604b224 [RISCV] Add support for XCVsimd extension in CV32E40P
Implement XCVsimd intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153721
2023-07-28 16:52:32 +08:00
Jun Sha (Joshua)
e56bf13317 [RISCV] Remove some instructions from Zvfbfwma by implying Zfbfmin according to the latest spec
According to the latest spec, Zvfbfwma requires Zvfbfmin and Zvfbfmin requires Zfbfmin, with FLH/FSH/FMV.H.X/HMV.X.H removed from Zvfbfwma.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155916
2023-07-28 15:52:03 +08:00
Roger Ferrer Ibanez
31747668aa [Docs] Fix code-blocks missing a colon and a newline
Fix syntax issues in the reStructuredText file that prevented rendering them.

Differential Revision: https://reviews.llvm.org/D156438
2023-07-28 05:36:49 +00:00
Qihan Cai
092e60a3fc [RISCV] Add support for XCValu extension in CV32E40P
Implement XCValu intrinsics for CV32E40P according to the specification.

This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153748
2023-07-28 11:37:31 +08:00
Bjorn Pettersson
9a53fe50f4 [LangRef] Fix typo in example describing memory layout of a vector. NFC
The example describing bitcasts (and memory layout) involving
vector types was incorrect for little endian.

This was reported in https://reviews.llvm.org/D94964
2023-07-28 01:00:30 +02:00
Maksim Kita
6af131abea [AggressiveInstCombine][Docs] Update pass documentation
Updated AggressiveInstCombine pass documentation because now AggressiveInstCombine can modify CFG.
Introduced in D154725.

Differential Revision: https://reviews.llvm.org/D156134
2023-07-26 19:33:31 +03:00
Shivam Gupta
64d19542e7 [LIT] Added an option to llvm-lit to emit the necessary test coverage data, divided per test case
This patch is the first part of https://llvm.org/OpenProjects.html#llvm_patch_coverage.

We have first define a new variable LLVM_TEST_COVERAGE which when set, pass --per-test-coverage option to
llvm-lit which will help in setting a unique value to LLVM_PROFILE_FILE for each RUN. So for example
coverage data for test case llvm/test/Analysis/AliasSet/memtransfer.ll will be emitted as
build/test/Analysis/AliasSet/memtransfer0.profraw

Reviewed By: hnrklssn

Differential Revision: https://reviews.llvm.org/D154280
2023-07-26 16:47:17 +05:30
Florian Mayer
6cc9244baa Enable hwasan-use-after-scope by default
This has been in use for a long time without any issues.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D156267
2023-07-25 17:36:15 -07:00
Thomas Köppe
6f1395a1fe [llvm-objcopy] --set-section-flags: allow "large" to add SHF_X86_64_LARGE
Currently, objcopy cannot set the new flag SHF_X86_64_LARGE. This change introduces the named flag "large" which translates to that section flag.

An "invalid argument" error is produced if a user attempts to set the flag on an architecture other than X86_64.

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D153262
2023-07-25 09:47:02 -07:00
Tobias Hieta
4706251a31
Clear release notes for 18.x 2023-07-25 13:58:49 +02:00
Matt Arsenault
395cd33ba8 AMDGPU: Remove trailing whitespace from documentation 2023-07-25 07:54:11 -04:00
Matt Arsenault
e3fd8f83a8 AMDGPU: Correctly expand f64 sqrt intrinsic
rocm-device-libs and llpc were avoiding using f64 sqrt
intrinsics in favor of their own expansions. Port the
expansion into the backend. Both of these users should be
updated to call the intrinsic instead.

The library and llpc expansions are slightly different.
llpc uses an ldexp to do the scale; the library uses a multiply.

Use ldexp to do the scale instead of the multiply.
I believe v_ldexp_f64 and v_mul_f64 are always the same number of
cycles, but it's cheaper to materialize the 32-bit integer constant
than the 64-bit double constant.

The libraries have another fast version of sqrt which will
be handled separately.

I am tempted to do this in an IR expansion instead. In the IR
we could take advantage of computeKnownFPClass to avoid
the 0-or-inf argument check.
2023-07-25 07:54:11 -04:00
Weining Lu
6223050db8 [docs] Add llvm & clang release notes for LoongArch
Differential Revision: https://reviews.llvm.org/D156195
2023-07-25 17:06:12 +08:00
Freddy Ye
6d23a3faa4 [X86] Support -march=graniterapids-d and update -march=graniterapids
Reviewed By: pengfei, RKSimon, skan

Differential Revision: https://reviews.llvm.org/D155798
2023-07-25 13:48:31 +08:00
Kai Luo
f26af16e2c [PowerPC][AIX] Enable quadword atomics by default for AIX
On AIX, a libatomic supporting inline quadword atomic operations has been released, so that compatibility is not an issue now, we can enable quadword atomics by default.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D151312
2023-07-25 08:21:07 +08:00
Jacek Caban
7450e0c1d3 [yaml2obj] Add support for load config section data.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D149440
2023-07-24 20:41:20 +02:00
Pravin Jagtap
c48ed93cf8 [AMDGPU] Add llvm.amdgcn.wave.reduce.umin/umax Intrinsic.
When input to intrinsic is uniform value, reduced value is
same as input whereas if input value is divergent we need
to iterate over all active lanes of WaveFront to perform
the reduction.

The control flow for a `loop` has been set up, which
iterates over `only` active lanes to perform reduction.

Introduced WAVE_REDUCE_UMIN_PSEUDO_U32 and
WAVE_REDUCE_UMAX_PSEUDO_U32 Pseudos which
are lowered Post-ISel (in `EmitInstrWithCustomInserter `).

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D154858
2023-07-24 00:06:00 -04:00
Matt Arsenault
8406c3568a AMDGPU: Implement new 2ulp fdiv lowering
Extends the new frexp scaled reciprocal to the general case. The
reciprocal case is just the same thing when frexp of 1 is constant
folded. Could probably clean up the code to rely on that constant
folding.

Improves results for the IEEE path for the default OpenCL division. We
used to only emit the fdiv.fast intrinsic with a 2.5 ulp accuracy
threshold with DAZ, which uses explicit range checks. This gives us a
better fast option with the default IEEE behavior.
2023-07-21 18:55:42 -04:00
Matt Arsenault
8287f3af9d AMDGPU: Overhaul and improve rcp and rsq f32 formation
The highlight change is a new denormal safe 1ulp lowering which uses
rcp after using frexp to perform input scaling. This saves 2
instructions compared to other implementations which performed an
explicit denormal range change. This improves the OpenCL default, and
requires a flag for HIP. I don't believe there's any flag wired up for
OpenMP to emit the necessary fpmath metadata.

This provides several improvements and changes that were hard to
separate without regressing one case or another. Disturbingly the
OpenCL conformance test seems to have the reciprocal test commented
out. I locally hacked it back in to test this.

Starts introducing f32 rsq intrinsics in AMDGPUCodeGenPrepare. Like
the rcp case, we could do this in codegen if !fpmath were preserved
(although we would lose some computeKnownFPClass tricks). Start
requiring contract flags to form rsq. The rsq fusion actually improves
the result from ~2ulp to ~1ulp. We have some older fusion in codegen
which only keys off unsafe math which should be refined.

Expand rsq patterns by checking for denormal inputs and pre/post
multiplying like the current library code does. We also take advantage
of computeKnownFPClass to avoid the scaling when we can statically
prove the input cannot be a denormal. We could do the same for the rcp
case, but unlike rsq a large input can underflow to denormal. We need
additional upper bound exponent checks on the input in order to do the
same for rcp.

This rsq handling also now starts handling the negated case. We
introduce rsq with an fneg. In the case the fneg doesn't fold into its
user, it's a neutral change but provides improvement if it is foldable
as a source modifier.

Also starts respecting the arcp attribute properly, and more strictly
interprets afn. We were previously interpreting afn as implying you
could do the reciprocal expansion of an fdiv. The codegen handling of
these also needs to be revisited.

This also effectively introduces the optimization
combineRepeatedFPDivisors enables, just done in the IR instead (and
only for f32).

This is almost across the board better. The one minor regression is
for gfx6/buggy frexp case where for multiple reciprocals, we could
previously reuse rematerialized constants per instance (it's neutral
for a single rcp).

The fdiv.fast and sqrt handling need to be revisited next.

https://reviews.llvm.org/D155593
2023-07-21 16:35:53 -04:00
Shivam Gupta
db04f018bb Revert "[LIT] Added an option to llvm-lit to emit the necessary test coverage data, divided per test case"
This reverts commit d8e26bccb3016d255298b7db78fe8bf05dd880b2.
Test case are meant to run only when LLVM_INDIVIDUAL_TEST_COVERAGE is set.
2023-07-21 15:59:56 +05:30
Shivam Gupta
d8e26bccb3 [LIT] Added an option to llvm-lit to emit the necessary test coverage data, divided per test case
This patch is the first part of https://llvm.org/OpenProjects.html#llvm_patch_coverage.

We have first define a new variable LLVM_TEST_COVERAGE which when set, pass --emit-coverage option to
llvm-lit which will help in setting a unique value to LLVM_PROFILE_FILE for each RUN. So for example
coverage data for test case llvm/test/Analysis/AliasSet/memtransfer.ll will be emitted as
build/test/Analysis/AliasSet/memtransfer.profraw

Reviewed By: hnrklssn

Differential Revision: https://reviews.llvm.org/D154280
2023-07-21 15:23:01 +05:30
wangpc
91ccbc6c1c [TableGen] Support named arguments
We provide a way to specify arguments in the form of `name=value`
so that we don't have to specify all optional arguments before the
one we'd like to change. Required arguments can alse be specified
in this way.

Note that the argument can only be specified once regardless of
the way (named or positional) to specify and positional arguments
should be put before named arguments.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152998
2023-07-20 16:03:17 +08:00
Freddy Ye
1c154bd755 [X86] Add AVX-VNNI-INT16 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155145
2023-07-20 14:31:16 +08:00
Freddy Ye
049d6a3f42 [X86] Add SM4 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155148
2023-07-20 13:35:15 +08:00
Freddy Ye
c6f66de21a [X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D155147
2023-07-20 10:24:16 +08:00
Freddy Ye
fc3b7874b6 [X86] Add SHA512 instructions.
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D155146
2023-07-20 09:44:44 +08:00
Craig Topper
3055c5815a [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Differential Revision: https://reviews.llvm.org/D155668
2023-07-19 10:03:57 -07:00
pvanhout
b50fe313e8 [TableGen] Deprecate old GI Combiner Emitter
Will be removed in a month or so.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D154939
2023-07-19 13:17:02 +02:00
Freddy Ye
cb11f97eb6 [X86] Add PBNDKB instruction.
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155142
2023-07-19 16:15:03 +08:00
Aiden Grossman
3336836dc2 [Docs][llvm-exegesis] Add documentation for memory annotations
Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D151039
2023-07-18 10:23:07 -07:00
Louis Dionne
49b209d5cc [lit] Remove the --no-indirectly-run-check option
This option had originally been added in D83069 to allow disabling the
check that something is going to get run at all when a specific test name
is used on the command-line. Since we now use getTestsForPath() (from D151664)
to get the tests to run for a specific path, we don't need a specific check
for this anymore -- Lit will produce the same complaint it would produce if
you provided a directory with no tests.

If one needs to run a specific test on the command-line and the Lit
configuration would normally not include that test, the configuration
should be set up as a "standalone" configuration or it should be fixed
to allow for that test to be found (i.e. probably fix the allowed test
suffixes).

Differential Revision: https://reviews.llvm.org/D153967
2023-07-17 17:59:15 -04:00
Jay Foad
92542f2a40 [AMDGPU] Add targets gfx1150 and gfx1151
This is the target definition only. Currently they are treated the same
as GFX 11.0.x.

Differential Revision: https://reviews.llvm.org/D155429
2023-07-17 13:06:12 +01:00
Martin Storsjö
c6bd873403 [CMake] Switch the CMP0091 policy (MSVC_RUNTIME_LIBRARY) to the new behaviour
With the new behaviour, the /MD or similar options aren't added to
e.g. CMAKE_CXX_FLAGS_RELEASE, but are added separately by CMake.
They can be changed by the cmake variable
CMAKE_MSVC_RUNTIME_LIBRARY or with the target property
MSVC_RUNTIME_LIBRARY.

LLVM has had its own custom CMake flags, e.g. LLVM_USE_CRT_RELEASE,
which affects which CRT is used for release mode builds. Deprecate
these and direct users to use CMAKE_MSVC_RUNTIME_LIBRARY directly
instead (and do a best effort attempt at setting CMAKE_MSVC_RUNTIME_LIBRARY
based on the existing LLVM_USE_CRT_ flags). This only handles the
simple cases, it doesn't handle multi-config generators with
different LLVM_USE_CRT_* variables for different configs though,
but that's probably fine - we should move over to the new upstream
CMake mechanism anyway, and push users towards that.

Change code in compiler-rt, that previously tried to override the
CRT choice to /MT, to set CMAKE_MSVC_RUNTIME_LIBRARY instead of
meddling in the old variables.

This resolves the policy issue in
https://github.com/llvm/llvm-project/issues/63286, and should
handle the issues that were observed originally when the
minimum CMake version was bumped, in
https://github.com/llvm/llvm-project/issues/62719 and
https://github.com/llvm/llvm-project/issues/62739.

Differential Revision: https://reviews.llvm.org/D155233
2023-07-17 09:59:05 +03:00
Lang Hames
8b26a81a23 [docs][JITLink] Update JITLink COFF/x86-64 backend status.
The COFF/x86-64 backend has been usable since LLVM 16.
2023-07-16 09:12:57 -07:00
Lang Hames
2f38604c79 [docs] Update JITLink's support matrix in the JITLink doc. 2023-07-15 17:20:52 -07:00
Jon Chesterfield
6043d4dfec [amdgpu] Accept an optional max to amdgpu-lds-size attribute for use in PromoteAlloca 2023-07-15 21:37:21 +01:00
Farid Zakaria
6fa8d11034 [docs] GettingStarted.rst cmake should reference build
The next sections in GettingStarted assume you are still in the root
directory llvm-project when using ninja.

Make the `cmake --build` command match it as well.

Note: I am a new cmake user and this confused me.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D153727
2023-07-15 11:36:13 -07:00
Zhongyunde
7203286329 [LangRef] vscale_range implies the vscale is power-of-two
According the discuss on D154953, we need to make the LangRef change
before the optimization relied on the new behaviour:
      vscale_range implies vscale is a power-of-two value, parse of the
  attribute to reject values that are not a power-of-two.

Thanks nikic for the wonderful summary of discussing on D154953:
To provide a bit more context here. We would like to have power of two vscale exposed in a target-independent way, so we can make use of this in places like ValueTracking, just like we currently do the vscale range. Some options that have been discussed are:
  - Remove support for non-power-of-two vscales entirely. (This is my personal preference, but this is hard to undo if it turns out someone does need them.)
  - Add an extra attribute vscale_pow2, or a data layout property.
  - Make vscale_range imply power-of-two vscale, as a compromise solution (what this patch does). This would be relatively easy to turn into one of the two above at a later point.

Reviewed By: paulwalker-arm, nikic, efriedma
Differential Revision: https://reviews.llvm.org/D155193
2023-07-15 09:13:48 +08:00
Simon Cook
4083ecfd7f [RISCV] Cleanups in CORE-V (xcv) extensions
This is a mostly NFC change cleaning up and clarifying components of the
in-tree CORE-V (xcv*) extensions following discussions on the remaining
extensions.

This makes the following changes to the xcbitmanip and xcvmac support:

1. Add missing extensions from RISCVISAInfo, such that they can be
   supported in clang's -march option.
2. Clarify the extension version number is 1.0.0 in documentation.
3. Clarify the extensions are by OpenHW Group, and the capitilization
   of the CORE-V extension family.
4. Add CORE-V to extension name in RISCVFeatures, both to be consistent
   with other vendors, and also better distinguish e.g. CORE-V bit
   manipulation vs RISC-V's standard Zb extensions.

Differential Revision: https://reviews.llvm.org/D155283
2023-07-14 18:21:08 +01:00
Nikita Popov
53717cabf8 [IR] Remove -opaque-pointers option
The test migration to opaque pointers has finished, so we can finally
drop typed pointer support from LLVM \o/

This removes the ability to disable typed pointers, as well as the
-opaque-pointers option, but otherwise doesn't yet touch any API
surface. I'll leave deprecation/removal of compatibility APIs to
future changes.

This also drops a few tests: These are either testing errors that
only occur with typed pointers, or type linking behavior that, to
the best of my knowledge, only applies to typed pointers.

Note that this will break some tests in the experimental SPIRV
backend, because the maintainers have failed to update their tests
in a reasonable time-frame, despite multiple warnings. In accordance
with our experimental target policy, this is not a blocking concern.
This issue is tracked at https://github.com/llvm/llvm-project/issues/60133.

Differential Revision: https://reviews.llvm.org/D155079
2023-07-14 09:07:11 +02:00
Jon Chesterfield
74e928a081 [amdgpu][lds] Remove recalculation of LDS frame from backend
Do the LDS frame calculation once, in the IR pass, instead of repeating the work in the backend.

Prior to this patch:
The IR lowering pass sets up a per-kernel LDS frame and annotates the variables with absolute_symbol
metadata so that the assembler can build lookup tables out of it. There is a fragile association between
kernel functions and named structs which is used to recompute the frame layout in the backend, with
fatal_errors catching inconsistencies in the second calculation.

After this patch:
The IR lowering pass additionally sets a frame size attribute on kernels. The backend uses the same
absolute_symbol metadata that the assembler uses to place objects within that frame size.

Deleted the now dead allocation code from the backend. Left for a later cleanup:
- enabling lowering for anonymous functions
- removing the elide-module-lds attribute (test churn, it's not used by llc any more)
- adjusting the dynamic alignment check to not use symbol names

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D155190
2023-07-13 23:54:38 +01:00
Fangrui Song
a4d1259e61 [llvm-objdump] Default to --mcpu=future for PPC32
Extend D127824 to the 32-bit Power architecture.
AFAICT GNU objdump -d dumps all instructions for 32-bit as well.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D155114
2023-07-12 18:24:18 -07:00
Aaron Ballman
0a6dfd40a6 Remove a stale note; NFC
We've completed the transition from SVN to Git, and the listed projects
are not included in the repository.
2023-07-12 15:56:59 -04:00
Aaron Ballman
a3bb2fdd5a Fix RST title underlining; NFC
This wasn't causing any bots to fail, so is just minor cleanup.
2023-07-12 15:56:31 -04:00
Sameer Sahasrabuddhe
da61c865e7 [RFC] Introduce convergence control intrinsics
This is a reboot of the original design and implementation by
Nicolai Haehnle <nicolai.haehnle@amd.com>:
https://reviews.llvm.org/D85603

This change also obsoletes an earlier attempt at restarting the work on
convergence tokens:
https://reviews.llvm.org/D104504

Changes relative to D85603:

 1. Clean up the definition of a "convergent operation", a convergent
    call and convergent function.
 2. Clean up the relationship between dynamic instances, sets of threads and
    convergence tokens.
 3. Redistribute the formal rules into the definitions of the convergence
    intrinsics.
 4. Expand on the semantics of entering a function from outside LLVM,
    and the environment-defined outcome of the entry intrinsic.
 5. Replace the term "cycle" with "closed path". The static rules are defined
    in terms of closed paths, and then a relation is established with cycles.
 6. Specify that if a function contains a controlled convergent operation, then
    all convergent operations in that function must be controlled.
 7. Describe an optional procedure to infer tokens for uncontrolled convergent
    operations.
 8. Introduce controlled maximal convergence-before and controlled m-converged
    property as an update to the original properties in UniformityAnalysis.
 9. Additional constraint that a cycle heart can only occur in the header of a
    reducible cycle (natural loop).

Reviewed By: nhaehnle

Differential Revision: https://reviews.llvm.org/D147116
2023-07-12 12:31:42 +05:30