7038 Commits

Author SHA1 Message Date
Hal Finkel
01271c6022 Don't reserve R2 on Darwin/PPC
Now that only the register-scavenger version of the CR spilling code remains,
we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in
any case where the System V ABI uses it (R0 is special architecturally, and so
is reserved under all common ABIs).

A few test cases needed to be updated to reflect the register-allocation changes.

llvm-svn: 176868
2013-03-12 15:18:14 +00:00
NAKAMURA Takumi
e781913ac4 llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.
llvm-svn: 176835
2013-03-11 23:16:30 +00:00
David Blaikie
47922fb006 Upgrading debug info test cases to be (more) compatible with the current debug info format.
These cases were found by further work to remove support for debug info
versioning. Common cleanups (other than changing the version info in the tag
field) included adding the last parameter to compile_units (recently added for
fission support) and other cases of trailing fields in lexical blocks, compile
units, and subprograms.

llvm-svn: 176834
2013-03-11 22:37:40 +00:00
David Blaikie
789beb5300 Remove duplicate test contents.
llvm-svn: 176831
2013-03-11 22:10:14 +00:00
Nick Lewycky
48beb21185 Fix a crasher newly introduced in r176659/r176649, where fast-isel tries to
lower an expect intrinsic that is a constant expression.

llvm-svn: 176830
2013-03-11 21:44:37 +00:00
Vincent Lejeune
e5ecf10a02 R600: Fix JUMP handling so that MachineInstr verification can occur
This allows R600 Target to use the newly created -verify-misched llc flag

llvm-svn: 176819
2013-03-11 18:15:06 +00:00
NAKAMURA Takumi
a60c7a0f4b llvm/test/CodeGen/X86/handle-move.ll: Mark it as XFAIL:cygming. Investigating.
llvm-svn: 176808
2013-03-11 16:30:26 +00:00
NAKAMURA Takumi
1e02e73c30 Suppress atomic(32|64).ll as XFAIL on win32 codegen. Investigating.
llvm-svn: 176798
2013-03-11 08:39:48 +00:00
Lang Hames
82d48e7fb0 Remove date from test case file name. The PR number provides a unique ID already.
llvm-svn: 176796
2013-03-11 03:49:23 +00:00
Lang Hames
be3d971143 Don't glue users to extract_subreg when selecting the llvm.arm.ldrexd
intrinsic - it can cause impossible-to-schedule subgraphs to be
introduced.

PR15053.

llvm-svn: 176777
2013-03-09 22:56:09 +00:00
Benjamin Kramer
01b75cc0f2 Test case hygiene.
llvm-svn: 176772
2013-03-09 18:25:40 +00:00
Jan Wen Voung
7857a64909 Disable statistics on Release builds and move tests that depend on -stats.
Summary:
Statistics are still available in Release+Asserts (any +Asserts builds),
and stats can also be turned on with LLVM_ENABLE_STATS.

Move some of the FastISel stats that were moved under DEBUG()
back out of DEBUG(), since stats are disabled across the board now.

Many tests depend on grepping "-stats" output.  Move those into
a orig_dir/Stats/. so that they can be marked as unsupported
when building without statistics.

Differential Revision: http://llvm-reviews.chandlerc.com/D486

llvm-svn: 176733
2013-03-08 22:56:31 +00:00
Jakob Stoklund Olesen
8d1aaf21cf Rewrite the physreg part of findLastUseBefore().
To find the last use of a register unit, start from the bottom and scan
upwards until a user is found.

<rdar://problem/13353090>

llvm-svn: 176706
2013-03-08 18:08:57 +00:00
Tom Stellard
5e524897ed R600: Optimize another selectcc case
fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
     selectcc x, y, a, b, cc

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176700
2013-03-08 15:37:11 +00:00
Tom Stellard
2add82de09 R600: Improve custom lowering of select_cc
Two changes:
1. Prefer SET* instructions when possible
2. Handle the CND*_INT case with floating-point args

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176699
2013-03-08 15:37:09 +00:00
Tom Stellard
492ebeabe9 R600: Change operation action from Custom to Expand for BR_CC
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176698
2013-03-08 15:37:07 +00:00
Tom Stellard
e8f9f2877b R600: Change operation action from Custom to Expand for SETCC
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176697
2013-03-08 15:37:05 +00:00
Tom Stellard
d93ef7afaa LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCC
llvm-svn: 176695
2013-03-08 15:37:02 +00:00
Vincent Lejeune
2bc2730765 R600: Change addresspace in fold-kcache.ll
AddressSpace definition has changed in a previous commit, reflect it
to avoid false failure.

llvm-svn: 176693
2013-03-08 15:34:07 +00:00
Tim Northover
c8f1a5de9f AArch64: specify full triple in test as only Linux works for now.
llvm-svn: 176692
2013-03-08 15:27:30 +00:00
Christian Konig
21442994a7 R600/SI: adjust test to recent changes
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176691
2013-03-08 14:44:00 +00:00
Jyotsna Verma
7825e064b9 Hexagon: Add patterns for zero extended loads from i1->i64.
llvm-svn: 176689
2013-03-08 14:15:15 +00:00
Tim Northover
95f4892d4c AArch64: expand sincos operations, we don't support them.
Patch based on Mans Rullgard's.

llvm-svn: 176688
2013-03-08 13:55:07 +00:00
David Blaikie
e7838a4c53 Another test fix for r176671.
llvm-svn: 176679
2013-03-08 02:27:40 +00:00
David Blaikie
d17cfedf8b Couple of test fixes for r176671.
Not sure why these aren't failing on my linux machine, but this should cover
it.

llvm-svn: 176678
2013-03-08 02:26:16 +00:00
Bill Wendling
2d915e2c15 Revert r176154 in favor of a better approach.
Code generation makes some basic assumptions about the IR it's been given. In
particular, if there is only one 'invoke' in the function, then that invoke
won't be going away. However, with the advent of the `llvm.donothing' intrinsic,
those invokes may go away. If all of them go away, the landing pad no longer has
any users. This confuses the back-end, which asserts.

This happens with SjLj exceptions, because that's the model that modifies the IR
based on there being invokes, etc. in the function.

Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will
give us a CFG that the back-end won't be confused about. If all of the invokes
in a function are removed, then the SjLj EH prepare pass won't insert the bogus
code the relies upon the invokes being there.
<rdar://problem/13228754&13316637>

llvm-svn: 176677
2013-03-08 02:21:08 +00:00
David Blaikie
e5a2f704a4 Upgrade tests to the latest debug info format.
Mostly this is just changing the named metadata (llvm.dbg.sp, llvm.dbg.gv,
llvm.dbg.<func>.lv, etc -> llvm.dbg.cu), adding a few fields to older records
(DIVariable: flags/inlined-at, DICompileUnit: sp/gv/types,
DISubprogram: local variables list)

The tests to update were discovered by a change I'm working on to remove debug
info version support - so any tests using old debug info versions I haven't
updated probably are bad tests or just not actually designed to test debug
info.

llvm-svn: 176671
2013-03-08 00:23:31 +00:00
Chad Rosier
9c1796f877 [fast-isel] Add support for the expect intrinsic.
rdar://13370942

llvm-svn: 176649
2013-03-07 20:42:17 +00:00
Jyotsna Verma
c7dcc2fbc5 Hexagon: Handle i8, i16 and i1 Var Args.
llvm-svn: 176647
2013-03-07 20:28:34 +00:00
Jyotsna Verma
2ba0c0b927 Hexagon: Add support to lower block address.
llvm-svn: 176637
2013-03-07 19:10:28 +00:00
Benjamin Kramer
5e5fd6bb4f Move testcase, this is testing extraction not inserting.
llvm-svn: 176635
2013-03-07 18:51:02 +00:00
Benjamin Kramer
2c3d0df8ee X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.
That can usually be lowered efficiently and is common in sandybridge code.
It would be nice to do this in DAGCombiner but we can't insert arbitrary
BUILD_VECTORs this late.

Fixes PR15462.

llvm-svn: 176634
2013-03-07 18:48:40 +00:00
Jim Grosbach
48a91abc10 SDAG: Handle scalarizing an extend of a <1 x iN> vector.
Just scalarize the element and rebuild a vector of the result type
from that.

rdar://13281568

llvm-svn: 176614
2013-03-07 05:47:54 +00:00
Michael Liao
d5cac37dc5 Fix two remaining issue after fixing PR15355 when CMOV is not available
- Phi nodes should be replaced/updated after lowering CMOV into branch
  because 'mainMBB' updating operand in Phi node is changed.
- Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as
  we will reuse the EFLAGS generated before the 1st lowered CMOV, which
  won't clobber EFLAGS. However, we need explicitly specify that.
- '-attr=-cmov' test case are added.

llvm-svn: 176598
2013-03-07 01:01:29 +00:00
Akira Hatanaka
0f693a8a77 [mips] Custom-legalize BR_JT.
In N64-static, GOT address is needed to compute the branch address.

llvm-svn: 176580
2013-03-06 21:32:03 +00:00
Akira Hatanaka
a9cf03fbd7 [mips] Add a line which checks function name. Rename file.
llvm-svn: 176543
2013-03-06 01:58:03 +00:00
Michael Liao
da22b30be5 Fix PR15355
- Clear 'mayStore' flag when loading from the atomic variable before the
  spin loop
- Clear kill flag from one use to multiple use in registers forming the
  address to that atomic variable
- don't use a physical register as live-in register in BB (neither entry
  nor landing pad.) by copying it into virtual register

(patch by Cameron Zwarich)

llvm-svn: 176538
2013-03-06 00:17:04 +00:00
Akira Hatanaka
1454ed8ad3 [mips] Remove android calling convention.
This calling convention was added just to handle functions which return vector
of floats. The fix committed in r165585 solves the problem.

llvm-svn: 176530
2013-03-05 23:22:30 +00:00
Akira Hatanaka
e092f72956 [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets
returned in registers $2 and $4.

llvm-svn: 176527
2013-03-05 22:54:59 +00:00
Akira Hatanaka
5f3ba9e595 [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
handle fp128 returns.

llvm-svn: 176523
2013-03-05 22:41:55 +00:00
Akira Hatanaka
3b7391d140 [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating
point registers.

llvm-svn: 176521
2013-03-05 22:20:28 +00:00
Akira Hatanaka
4b634fa3b3 [mips] Correct handling of fp128 (long double) formals and read long double
parameters from floating point registers if target is mips64 hard float.

llvm-svn: 176520
2013-03-05 22:13:04 +00:00
Jyotsna Verma
457801f7ab reverting patch 176508.
llvm-svn: 176513
2013-03-05 20:29:23 +00:00
Jyotsna Verma
7179e712dd Hexagon: Add support for lowering block address.
llvm-svn: 176508
2013-03-05 19:37:46 +00:00
Jyotsna Verma
0eeea14e3e Hexagon: Expand addc, adde, subc and sube.
llvm-svn: 176505
2013-03-05 19:04:47 +00:00
Jyotsna Verma
f4e324f4fb Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499
2013-03-05 18:42:28 +00:00
Vincent Lejeune
3b6f20e944 R600: Turn BUILD_VECTOR into Reg_Sequence
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176487
2013-03-05 15:04:49 +00:00
Vincent Lejeune
a199d01e4d R600: Use MUL_IEEE for trig/fdiv intrinsic
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176485
2013-03-05 15:04:37 +00:00
NAKAMURA Takumi
3ae057c6ab llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit -mtriple=mips64el-unknown-unknown to appease win32.
FIXME: Is it expected for win32 to affect mips targets?
llvm-svn: 176471
2013-03-05 02:18:59 +00:00
NAKAMURA Takumi
cc91d50289 llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts.
llvm-svn: 176470
2013-03-05 02:18:52 +00:00