529240 Commits

Author SHA1 Message Date
erichkeane
d5cec386c1 [OpenACC] Implement 'cache' construct AST/Sema
This statement level construct takes no clauses and has no associated
statement, and simply labels a number of array elements as valid for
caching. The implementation here is pretty simple, but it is a touch of
a special case for parsing, so the parsing code reflects that.
2025-03-03 13:57:23 -08:00
Thurston Dang
d6599fc3b9
[msan][NFC] Rename NEON tests and fix comment (#127926)
This renames the neon_* tests to be more consistent with the original files that they were forked from. This makes it easier for maintainers to see which test files may need to be ported to MSan.

It also fixes the header comment for llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll (instrumentation was updated in #126136 aka e9e6ba6a5e2a4ca7386861136196903febb9968b, but the comment was not).
2025-03-03 13:54:39 -08:00
Mats Jun Larsen
a21ae2f04f
[CodeGen][ObjCGNU] Replace PointerType::getUnqual(Type) with opaque pointer version (NFC) (#128715)
Follow-up to #123569
2025-03-03 22:51:00 +01:00
Jacek Caban
f2473bc31e
[LLD][COFF] Support -aligncomm directives on ARM64X (#129513) 2025-03-03 22:48:20 +01:00
Longsheng Mou
7d650bf331
[mlir][tosa] Fix several bugs in DepthwiseConv2DIsMul (#129210)
This PR fixes several bugs in `DepthwiseConv2DIsMul`:
- The DepthwiseConv2DOp should restrict the types to integer or float to
prevent a crash.
- `notifyMatchFailure` should be called before creating the new
operations.
2025-03-03 13:45:00 -08:00
Augie Fackler
fd9a882ce3 [bazel] add missing header to bolt build file 2025-03-03 16:41:14 -05:00
Jacek Caban
2d0eb5df4f
[LLD][COFF] Add support for -includeglob on ARM64X (#129515)
Include symbols from both symbol tables.
2025-03-03 22:39:42 +01:00
Krzysztof Parzyszek
8f971ca1d9
[flang] Move DumpEvaluateExpr from Lower to Semantics (#128723)
Since evaluate::Expr can show up in the parse tree in the semantic
analysis step, make it possible to dump its structure in the Semantics
module.

The Lower module depends on Semantics, so the code is still accessible
in it.
2025-03-03 15:38:42 -06:00
Michael Spencer
1c4e0f6a54
[clang] Add #pragma clang __debug module_lookup (#129158)
This can be used to trigger implicit module map lookup without also
importing the module. This can be useful for debugging as it avoids
loading the module map from the AST file, which has slightly different
semantics.
2025-03-03 13:28:10 -08:00
Kai Nacke
eee3db5421
[SystemZ] Change operand type for CKSM intrstruction. (#129572)
The current definition of the CKSM instruction uses GR64 for the first
operand. However, according to the Principles Of Operation the bits 0-31
of the first operand always remain unchanged. This PR changes the first
operand to GR32 to model this.
This has no further implication as this instruction is not used during
code generation.
2025-03-03 16:17:29 -05:00
Augie Fackler
2cb7b4e0cd [bazel] fix missing dep on //llvm:config in //lldb:Core 2025-03-03 16:15:21 -05:00
JP Hafer
36a2d7bf1b
[AsmWriter] Combine IsConstant and GetConstant (NFCI) (#129288)
There was an assert in GetConstant checked if Bound is constant.
However, GetConstant was only called when IsConstant==true.

This refactor attempts to get rid of the assert by combining GetConstant
and IsContstant.
2025-03-03 22:04:09 +01:00
Craig Topper
2b509ecf2d [AST] Reorder fields in FunctionTypeBitfields to avoid splitting a field across 32 bit boundary
Fixes #129521.
2025-03-03 13:01:08 -08:00
Florian Hahn
87f837cb26
[VPlan] Remove unneeded classof with VPHeaderRecipe args (NFC).
The extra classof implementation is not needed any longer.
2025-03-03 20:52:28 +00:00
LLVM GN Syncbot
9f879dea2e [gn build] Port b971d4d7c808 2025-03-03 20:44:45 +00:00
Maksim Panchenko
b971d4d7c8
[BOLT][AArch64] Add symbolizer for AArch64 disassembler. NFCI (#127969)
Add AArch64MCSymbolizer that symbolizes `MCInst` operands during
disassembly. The symbolization was previously done in
`BinaryFunction::disassemble()`, but it is also required by
`scanExternalRefs()` for "lite" mode functionality. Hence, similar to
x86, I've implemented the symbolizer interface that uses
`BinaryFunction` relocations to properly create instruction operands. I
expect the result of the disassembly to be identical after the change.

AArch64 disassembler was not calling `tryAddingSymbolicOperand()` for
`MOV` instructions. Fix that. Additionally, the disassembler marks `ldr`
instructions as branches by setting `IsBranch` parameter to true. Ignore
the parameter and rely on `MCPlusBuilder` interface instead.

I've modified `--check-encoding` flag to check symolization of operands
of instructions that have relocations against them.
2025-03-03 12:44:28 -08:00
Alexander Shaposhnikov
39402cde61
[compiler-rt][ubsan] Refactor cast-overflow test (#129460)
This PR cleans up cast-overflow.cpp, more specifically:
1. avoid using undefined value as an exit code (old case `9`)
2. narrowing conversions are allowed to produce `inf` and they are
well-defined. Remove dead code (old case `8`)
3. the same applies to the conversion int -> float16. Remove dead code
(old case `7`)

See also
https://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html#:~:text=%2Dfsanitize%3Dfloat%2Dcast,to%20integer%20types.

Currently ubsan doesn't properly detect UB on float16 -> int casts, I
have a fix for that (will send as a separate PR).
2025-03-03 12:32:58 -08:00
Joseph Huber
4ca8ea8c97
[Clang] Fix GPU intrinsic helpers incorrectly sign extending (#129560)
Summary:
These return values are actually signed, meaning that casting will
extend it and then all the bits will be one.
2025-03-03 14:26:43 -06:00
Mirza Halilčević
1fc49ff593
[MLIR][AMDGPU] Add OCP FP8 support for new hardware (#127728)
(Continuing from #106160)

This PR addresses remaining review comments from the original PR.

Original PR Description
---
Upcoming hardware (gfx12 and some future gfx9) will support the OCP
8-bit float formats for their matrix multiplication intrinsics and
conversion operations, retaining existing opcodes and compiler builtins.

This commit adds support for these types to the MLIR wrappers around
such operations, ensuring that the OCP types aren't used to generate
those builtins on hardware that doesn't expect that format and,
conversely, to ensure that the pre-OCP formats aren't used on new
hardware.

---------

Signed-off-by: Mirza Halilcevic <mirza.halilcevic@amd.com>
Co-authored-by: Paul Fuqua <pf@acm.org>
Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak@amd.com>
2025-03-03 14:10:31 -06:00
Augie Fackler
08dc81bd29 [bazel] fixes to make Telemetry work in lldb
Previously telemetry was optional at build-time in such a way that none
of it was built at all, but llvm/llvm-project@159b872b37 changed that
and now it's optional in a different way so we need to have it available
in the bazel BUILD graph.
2025-03-03 15:06:54 -05:00
Jean-Didier PAILLEUX
a9b2e31fb0
[flang] Define CO_REDUCE intrinsic procedure (#125115)
Define the intrinsic `CO_REDUCE` and add semantic checks.
A test was already present but was at `XFAIL`. It has been modified to
take new messages into the output.
2025-03-03 20:50:02 +01:00
Kelvin Li
83f8721201
[flang] handle passing bind(c) derived type by value for ppc64le and powerpc64-aix (#128780) 2025-03-03 14:43:43 -05:00
Brendan Sweeney
4fd5d935a3
[RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (#121017)
When Zalasr is enabled, it will emit the A7 atomic ABI tag. Zalasr is
the load-acquire and store-release extension, and the reason A7 (and
A6S) exists is to support it.

The A7 atomic ABI is compatible with A6S (which is what is currently
emitted as the tag), but A7 is not compatible with A6C, while A6C and
A6S are compatible.


https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc#risc-v-atomics-mappings


https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version
2025-03-03 11:34:52 -08:00
Alexey Bataev
41e58b6737 [SLP][NFC]Add a test for 2 spilled vector values spilled in diamond shaped control flow 2025-03-03 11:33:33 -08:00
Sarah Spall
25713ed85f
[HLSL] Add additional overloads for min and max to allow for mixed scalar and vector arguments (#129334)
Add additional overloads for min and max to support
min(vector<T,N>, T) and min(T, vector<T,N>)
max(vector<T,N>, T) and max(T, vector<T,N>)
Add tests
Closes #128231
2025-03-03 11:29:58 -08:00
Krzysztof Drewniak
dc1ff4145a
[mlir][tblgen] Migrate tests to properties for attributes, fix remove*Attr() (#123505)
The only in-tree user of `bit usePropertiesForAttributes = 0;` was a
series of tests for the output of -gen-op-{decls,defs}. This commit
updates those tests to match the rest of the repository.

In the short term, this is intended to enable testing upcoming updates
to collective builders. In the long term, this is a step in the removal
of usePropertiesForAttributes = 0.

One side effect of these tests updates was the realization that the
autogenerated implementations of removeFooAttr() were not returning the
value of the removed attribute. This issue has been addressed and the
tests have been updated to reflect the change. This is the only
functionality change in this PR.
2025-03-03 13:22:33 -06:00
alx32
28fc00b10e
[GSYM] Use debug line offsets during GSYM creation (#129196)
This patch introduces support for the `DW_AT_LLVM_stmt_sequence`
attribute in the GSYM DWARF transformer. With this change, the DWARF
GSYM creation process can now accurately associate debug information
with the correct functions, even when multiple functions have been
merged together.

The `macho-gsym-merged-callsites-dsym.yaml` test data is regenerated to
include the fixes in the DWARF linker
(https://github.com/llvm/llvm-project/pull/128953) and the test is
updated to check that debug data is correctly associated for merged
functions.
2025-03-03 11:22:16 -08:00
Nirvedh Meshram
70b95d1664
[mlir][linalg] Retain Op Type of linalg ops in fuseWithReshapeByExpansion pattern (#129128)
This PR preserve linalg Op types for certain named ops such as Fill,
Copy and Transpose instead of fusion always resulting in a generic Op.

---------

Signed-off-by: Nirvedh Meshram <nirvedh@gmail.com>
2025-03-03 13:20:29 -06:00
Stanislav Mekhanoshin
6c9a9d9fe2
[AMDGPU] Set inst_pref_size to maximum (#126981)
On gfx11 and gfx12 set initial instruction prefetch size to a
minimum of kernel size and maximum allowed value.

Fixes: SWDEV-513122
2025-03-03 10:40:31 -08:00
Timm Baeder
4dd29ebb8d
[clang][bytecode][NFC] Move incorrect LLVM_PREFERRED_TYPE attribute (#128740)
Looks like this was accidentally added after the bitfield and thus
didn't work.
2025-03-03 19:37:22 +01:00
Luke Hutton
079557c3d4
[mlir][tosa] Add verifiers for FFT2d and RFFT2d (#129273)
Adds checks for element types and input/output shapes.

Signed-off-by: Luke Hutton <luke.hutton@arm.com>
2025-03-03 10:26:19 -08:00
Amr Hesham
ab30df470a
[CIR] Upstream floating point literal expressions (#129304)
This change adds support for floating point literal expressions
2025-03-03 19:22:44 +01:00
Amr Hesham
af464c6d53
[Clang][diagnostics] Fix structured binding shadows template param loc (#129116)
Fix structured binding shadows template parameter location

Fixes: #129060
2025-03-03 19:22:28 +01:00
ofri frishman
6e59282235
[MLIR] Add pattern to bubble up tensor.extract_slice (#126898)
Add a pattern that bubbles up tensor.extract_slice through
tensor.expand_shape, and add a transform op to tensor dialect
to directly use this pattern.
This pattern enables tiling and fusing op chains which contain
tensor.expand_shape if added as a cleanup pattern of tile and fuse
utility.
Without this pattern that would not be possible, as
tensor.expand_shape does not implement the tiling interface.
In addition, registering this pattern as a cleanup pattern for
transform.structured.fuse.
The pattern was first implement in IREE project by
Quinn Dawkins and is being upstreamed.

---------

Co-authored-by: Quinn Dawkins <quinn.dawkins@gmail.com>
2025-03-03 18:20:50 +00:00
Rahul Joshi
f44c18a97d
[NFC][CodingStandard] Fix text style for C++ keywords (#128932)
Fix C++ keywords in Restrict Visibility section to use `` (inline
literal) markup to be consistent with the rest of the doc.
2025-03-03 10:18:12 -08:00
OverMighty
d9ac5d0be6
[libc][docs] Add links to Peter Smith's FOSDEM 2025 talk (#129555) 2025-03-03 19:15:21 +01:00
Fangrui Song
a0671758eb Reapply [MCExpr] Remove generic getVariantKindName and getVariantKindForName
They are error-prone as MCParser may parse a variant kind,
which cannot be handled by the target.

The replacement in MCAsmInfo should be used instead.

Follow-up to f244b8eed37a12539fb11b76e19ec7a7eb41dccc
2025-03-03 10:14:10 -08:00
Paul Osmialowski
8f4ee42d59
[libc++][test] extend XFAIL clauses to cover Amazon Linux too (#129377)
The default triple of Amazon Linux on AArch64 is aarch64-amazon-linux,
see issue highlighded by PR #109263, somewhat serious linker issues are
encountered if any other triple is being used.

Unfortunately, this makes XFAIL lines like
`XFAIL: target=aarch64{{.*}}-linux-gnu` ineffective, making it
impossible to complete all of the check-cxx on Amazon Linux without
failing.
2025-03-03 18:10:36 +00:00
jimingham
64c26c8f16
Fix a bug copying the stop hooks from the dummy target. (#129340)
We didn't also copy over the next stop hook id, which meant we would
overwrite the stop hooks from the dummy target with stop hooks set after
they are copied over.
2025-03-03 09:59:42 -08:00
Simon Pilgrim
44badc9810
[X86] combineConcatVectorOps - use isSplatValue helper instead of matching specific VBROADCAST opcodes. (#129556) 2025-03-03 17:59:15 +00:00
Slava Zakharin
a704e6587b
[flang] Added alternative inlining code for hlfir.cshift. (#129176)
Flang generates slower code for `CSHIFT(CSHIFT(PTR(:,:,I),sh1,1),sh2,2)`
pattern in facerec than other compilers. The first CSHIFT can be done
as two memcpy's wrapped in a loop for the second dimension.
This does require creating a temporary array, but it seems to be faster,
than the current hlfir.elemental inlining.

I started with modifying the new index computation in
hlfir.elemental inlining: the new arith.select approach does enable
some vectorization in LLVM, but on x86 it is using gathers/scatters
and does not give much speed-up.

I also experimented with LoopBoundSplitPass
and InductiveRangeCheckElimination for a simple (not chained) CSHIFT
case, but I could not adjust them to split the loop with a condition
on the value of the IV into two loops with disjoint iteration spaces.
I thought if I could do it, I would be able to keep the hlfir.elemental
inlining mostly untouched, and then adjust the hlfir.elemental inlining
heuristics for the facerec case.

Since I was not able to make these pass work for me, I added a special
case inlining for CSHIFT(ARRAY,SH,DIM=1) via hlfir.eval_in_mem.
If ARRAY is not statically known to have the contiguous leading
dimension, there is a dynamic check for contiguity, which allows
exposing it to LLVM and enabling the rewrite of the copy loops
into memcpys. This approach is stepping on the toes of LoopVersioning,
but it is helpful in facerec case.

I measured ~6% speed-up on grace, and ~4% on zen4.
2025-03-03 09:58:20 -08:00
Ellis Hoag
d2c4d1ec48
[memprof] Export __memprof_default_options_str on Darwin (#128920)
The `-memprof-runtime-default-options` LLVM flag introduced in
https://github.com/llvm/llvm-project/pull/118874 creates the
`__memprof_default_options_str` symbol with `WeakAnyLinkage` on Darwin.


fa0202169a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp (L573-L576)

This ensures Darwin passes `-exported_symbol
___memprof_default_options_str` to the linker so that the runtime
library has visibility into this symbol.

This will replace the earlier PR
https://github.com/llvm/llvm-project/pull/128615
2025-03-03 09:57:35 -08:00
Fangrui Song
0739ce88ef [MC] Port initializeVariantKinds to ARM COFF and SystemZ GOFF
... so that they use the target-specific variantKindDescs instead of the
generic MCExpr one (which will go away as it's error-prone).
2025-03-03 09:55:49 -08:00
Daniel Paoliello
e93cd15f9e
[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)
Not sure why this was disabled in the first place (dates back to
<fbe9c04c5f>),
but it appears to be working for me.
2025-03-03 09:54:28 -08:00
LLVM GN Syncbot
fc81e264f9 [gn build] Port 5d7d66ba0d1a 2025-03-03 17:31:14 +00:00
Abhilash Majumder
7c580893ea
[NVPTX] Add Intrinsics for discard.* (#128404)
[NVPTX] Add  Intrinsics for discard.*
This PR adds intrinsics for all variations of discard.*

* These intrinsics supports generic or global for all variations.
* The lowering is handled from nvvm to nvptx tablegen directly.
* Lit tests are added as part of discard.ll
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst.

For more information, refer to the PTX ISA

<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-discard>_.

---------

Co-authored-by: abmajumder <abmajumder@nvidia.com>
Co-authored-by: gonzalobg <65027571+gonzalobg@users.noreply.github.com>
2025-03-03 22:53:49 +05:30
Kazu Hirata
3919793889
[WebAssembly] Avoid repeated hash lookups (NFC) (#129469) 2025-03-03 09:18:36 -08:00
serge-sans-paille
f3d4d11547
[clang][cmake] Fix support for dynamic libraries in CLANG_BOLT
Simpler detection of dynamic library operands as the readelf one seems
to be unreliable (works on my setup, not on buildbots).

This is a follow-up to #127020
2025-03-03 18:05:18 +01:00
Nico Weber
86fc248ff6 [gn] port 50317ca13f6ad9 2025-03-03 12:02:55 -05:00
George Burgess IV
3ce92e1c4f
github: fix empty continuation line; remove trailing whitespace (#129535)
- Trailing whitespace shows up as red on my editor, so remove.
- Docker on my machine warns that having line continuations like:

```
  sudo \

  foo
```

is deprecated, and will become an error, so fix that up ahead of time.
2025-03-03 09:47:42 -07:00