Implement Xtensa S32C1I Option. Implement atomic_cmp_swap_32 operation
using s32c1i instruction. Use atomic_cmp_swap_32 operation and AtomicExpand
pass to implement atomics operations.
Implement Xtensa FP Option instructions and lowering
of the base FP operations with tests. Implement UR registers parsing.
Fix loading from constant pool callee, basic block, globaladdress and
jumptable addresses. Also fixed potential memory leakage when several
similar XtensaConstantPoolValue objects are created Fix lowering i32 immediate.
Implement basic support of the several simple Xtensa Options with 1-4
instructions for each option. The Sign Extend Option (SEXT). The NSA
Option. The Minimum/Maximum Integer 32-bit Option and Loop Option.
Fixed address operands, added OPERAND_PCREL to operands descriptions.
Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.
Note: I don't have commit access.
Implement lowering of the Mul/Div operations and also shift parts
operations. Implement lowering of the bit manipulations, like
ROT/SWAP/CTPOP/CTTZ/CTLZ.
This patch implements lowering of the GlobalAddress, BlockAddress,
JumpTable and BR_JT. Also patch adds legal support of the BR_CC
operation for i32 type.
Implement emitPrologue/emitEpilogue methods, determine/spill/restore
callee saved registers functionality with test. Also implement lowering
of the DYNAMIC_STACKALLOC/STACKSAVE/STACKRESTORE stack operations with
tests.
This PR provides implementation of the basic codegen infra such as
TargetFrameLowering, MCInstLower,
AsmPrinter, RegisterInfo, InstructionInfo, TargetLowering,
SelectionDAGISel.
Migrated from https://reviews.llvm.org/D145658
