12 Commits

Author SHA1 Message Date
Philip Reames
a0c7714525
[RISCV] Split div vs rem scheduling information [nfc] (#84385)
Allows a processor to define different latencies for the two operations.
2024-03-07 14:03:58 -08:00
Yingwei Zheng
89f87c3876
[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)
This patch implements the zabha (Byte and Halfword Atomic Memory
Operations) v1.0-rc1 extension.
See also https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc.
2024-01-31 17:06:43 +08:00
Yingwei Zheng
9c3c0e324f
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
This PR separate addend from FMA operands to support cascade FMA. In
some microarchitectures (e.g., ARM cortex-a72 and XiangShan-NanHu), FP
multiply-accumulate pipelines support late-forwarding of accumulate
operands, which reduces the latency of a sequence of multiply-accumulate
instructions.
See also #70232.
2023-10-26 13:00:36 +08:00
Michael Maitland
85e3875ad7 [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

This commit as previously reverted since it missed renaming that came
down after rebasing. This version of the commit fixes those problems.

Differential Revision: https://reviews.llvm.org/D158568
2023-08-24 19:21:36 -07:00
Michael Maitland
71bfec762b Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
This reverts commit 5b854f2c23ea1b000cb4cac4c0fea77326c03d43.

Build still failing.
2023-08-24 15:37:27 -07:00
Michael Maitland
5b854f2c23 [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

This commit as previously reverted since it missed renaming that came
down after rebasing. This version of the commit fixes those problems.

Differential Revision: https://reviews.llvm.org/D158568
2023-08-24 15:25:42 -07:00
Michael Maitland
4d27dffb43 Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
This reverts commit 030d33409568b2f0ea61116e83fd40ca27ba33ac.

This commit is causing build failures
2023-08-24 11:58:53 -07:00
Michael Maitland
030d334095 [TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
D150312 added a TODO:

TODO: consider renaming the field `StartAtCycle` and `Cycles` to
`AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
fact that resource allocation is now represented as an interval,
relatively to the issue cycle of the instruction.

This patch implements that TODO. This naming clarifies how to use these
fields in the scheduler. In addition it was confusing that `StartAtCycle` was
singular but `Cycles` was plural. This renaming fixes this inconsistency.

Differential Revision: https://reviews.llvm.org/D158568
2023-08-24 11:20:37 -07:00
Craig Topper
cdb91465e3 [RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
It was only used for the compressed instruction c.jr which expands
to jalr with rd=x0. Use WriteJalr instead to match jalr.
2023-06-25 21:59:27 -07:00
Craig Topper
a2a4b605e2 [RISCV] Split ReadSFB into ReadSFBJmp and ReadSFBALU.
The operands may need to be available at different times.
2023-06-23 16:52:45 -07:00
Jun Sha (Joshua)
100d2079f6 [RISCV] Add scheduling for Zfa instructions
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D148686
2023-04-20 13:46:34 +08:00
Dmitrii Petrov
c86a878e89 [RISCV] Add Syntacore SCR1 CPU model
SCR1 is available at https://github.com/syntacore/scr1

'syntacore-scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'syntacore-scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.

SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139302
2022-12-14 11:45:44 +03:00