267048 Commits

Author SHA1 Message Date
Paschalis Mpeis
e50c4c83b6
[AArch64][TLI] Add TLI mappings for ArmPL modf, sincos, sincospi (#83143)
ArmPL 24.04 release fixes a bug concerning these methods,
so now they can be re-introduced to TLI mappings.
2024-04-10 09:34:46 +01:00
Chia
469caa31e7
[RISCV] Use vwadd.vx for splat vector with extension (#87249)
This patch allows `combineBinOp_VLToVWBinOp_VL` to handle patterns like
`(splat_vector (sext op))` or `(splat_vector (zext op))`. Then we can
use `vwadd.vx` and `vwadd.w` for such a case.

### Source code
```
define <vscale x 8 x i64> @vwadd_vx_splat_sext(<vscale x 8 x i32> %va, i32 %b) {
     %sb = sext i32 %b to i64
     %head = insertelement <vscale x 8 x i64> poison, i64 %sb, i32 0
     %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
     %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
     %ve = add <vscale x 8 x i64> %vc, %splat
     ret <vscale x 8 x i64> %ve
}
```

### Before this patch
[Compiler Explorer](https://godbolt.org/z/sq191PsT4)
```
vwadd_vx_splat_sext:
  sext.w a0, a0
  vsetvli a1, zero, e64, m8, ta, ma
  vmv.v.x v16, a0
  vsetvli zero, zero, e32, m4, ta, ma
  vwadd.wv v16, v16, v8
  vmv8r.v v8, v16
  ret
```
### After this patch
```
vwadd_vx_splat_sext
  vsetvli a1, zero, e32, m4, ta, ma
  vwadd.vx v16, v8, a0
  vmv8r.v v8, v16
  ret
```
2024-04-10 15:26:17 +09:00
XChy
313a33b9df
[InstCombine] Reduce nested logical operator if poison is implied (#86823)
Fixes #76623
Alive2 proof: https://alive2.llvm.org/ce/z/gX6znJ (I'm not sure how to
write a proof for such transform, maybe there are mistakes)

In most cases, `icmp(a, C1) && (other_cond && icmp(a, C2))` will be
reduced to `icmp(a, C1) & (other_cond && icmp(a, C2))`, since latter
icmp always implies the poison of the former. After reduction, it's
easier to simplify the icmp chain.
Similarly, this patch does the same thing for `(A && B) && C --> A && (B
& C)`. Maybe we could constraint such reduction only on icmps if there
is regression in benchmarks.
2024-04-10 14:19:44 +08:00
Shih-Po Hung
3d985a6f1b
[RISCV][TTI] Scale the cost of Select with LMUL (#88098)
Use the Val type to estimate the instruction cost for SelectInst.
2024-04-10 14:18:15 +08:00
Congzhe
b0662a7a7d
[CodeMoverUtils] Enhance CodeMoverUtils to sink an entire BB (#87857)
When moving an entire basic block after `InsertPoint`, currently we
check each instruction whether their users are dominated by
`InsertPoint`, however, this can be improved such that even a user is
not dominated by `InsertPoint`, as long as it appears as a subsequent
instruction in the same BB, it is safe to move.

This patch is similar to commit 751be2a064f119af74c7b9b1e52bc904d8aa114d
that enhanced hoisting an entire BB, and this patch enhances sinking an
entire BB. Please refer to the added functionality in test case
`llvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp` that was not
supported without this patch.
2024-04-10 00:28:21 -04:00
Noah Goldstein
6c40d463c2 [X86] Use nneg flag when trying to convert uitofp -> sitofp
Closes #86694
2024-04-09 23:06:55 -05:00
Noah Goldstein
7013638978 [DAG] Add support for nneg flag with uitofp
Copy `nneg` flag when building `UINT_TO_FP` from `uitofp` and use
`nneg` flag in the one place we transform `UINT_TO_FP` -> `SINT_TO_FP`
if the operand is non-negative.
2024-04-09 23:06:55 -05:00
Noah Goldstein
84a5332a68 [X86] Add tests for uitofp nneg -> sitofp; NFC 2024-04-09 23:06:55 -05:00
Connor Sughrue
87e6f87fe7
[llvm][Support] Improvements to ListeningSocket functionality and documentation (#84710)
Improvements include
* Enable `ListeningSocket::accept` to timeout after a specified amount
of time or block indefinitely
* Enable `ListeningSocket::createUnix` to handle instances where the
target socket address already exists and differentiate between
situations where the existing file does and does not already have a
bound socket
* Doxygen comments

Functionality added for the module build daemon

---------

Co-authored-by: Michael Spencer <bigcheesegs@gmail.com>
2024-04-09 23:41:18 -04:00
Pengcheng Wang
8dc006ea40
[RISCV] Make EmitToStreamer return whether Inst is compressed
This is helpful to reduce calls of `RISCVRVC::compress` in #77337.

Reviewers: asb, lukel97, topperc

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/88120
2024-04-10 11:02:55 +08:00
Lei Wang
1aceee7bb6
Remove unused variable (#88223)
fix the CI
2024-04-09 19:25:08 -07:00
hanbeom
44c79da3ae
[InstCombine] Remove shl if we only demand known signbits of shift source (#79014)
This patch resolve TODO written in commit:
5909c67883

Proof: https://alive2.llvm.org/ce/z/C3VNoR
2024-04-10 11:19:09 +09:00
Shih-Po Hung
ee52add6cb
[RISCV][TTI] Implement cost of intrinsic active_lane_mask (#87931)
This patch uses the argument type to infer the LMUL cost for the index
generation, add, and comparison.
2024-04-10 10:08:33 +08:00
Lei Wang
892f01a743
Remove the assertion to unblock breakages (#88035)
as titled.
2024-04-09 18:53:09 -07:00
Evgenii Stepanov
e8a3b72272 [msan] Precommit tests.
Precommit tests for overflowing and saturating arithmetic intrinsics.
2024-04-09 16:32:48 -07:00
Noah Goldstein
9170e38575 Add support for nneg flag with uitofp
As noted when #82404 was pushed (canonicalizing `sitofp` -> `uitofp`),
different signedness on fp casts can have dramatic performance
implications on different backends.

So, it makes to create a reliable means for the backend to pick its
cast signedness if either are correct.

Further, this allows us to start canonicalizing `sitofp`- > `uitofp`
which may easy middle end analysis.

Closes #86141
2024-04-09 18:12:33 -05:00
Teresa Johnson
a332cfc986
[MemProf] Perform cloning for each allocation separately (#87112)
Restructures the cloning slightly to perform all cloning for each
allocation separately. The prior algorithm would sometimes miss cloning
opportunities in cases where trimmed cold contexts partially overlapped
with longer contexts for different allocations.

Most of the change is isolated to the helpers that move edges to new or
existing clones, which now support moving a subset of context ids.
2024-04-09 14:12:32 -07:00
Youngsuk Kim
b561fd3726
[docs] Fix broken link in Benchmarking docs (#88117)
Fixes #58813
2024-04-09 17:06:41 -04:00
Joseph Huber
470aefb240
[Offload][NFC] Remove omp_ prefix from offloading entries (#88071)
Summary:
These entires are generic for offloading with the new driver now. Having
the `omp` prefix was a historical artifact and is confusing when used
for CUDA. This patch just renames them for now, future patches will
rework the binary format to make it more common.
2024-04-09 15:50:15 -05:00
Noah Goldstein
71ef04d7cd [InstCombine] fold (icmp eq/ne (or disjoint x, C0), C1) -> (icmp eq/ne x, C0^C1)
Proof: https://alive2.llvm.org/ce/z/m3xoo_

Closes #87734
2024-04-09 15:38:18 -05:00
Noah Goldstein
5b58eb68ed [InstCombine] Add tests for folding (icmp eq/ne (or disjoint x, C0), C1); NFC 2024-04-09 15:38:18 -05:00
Florian Hahn
a8ec1eb843
[VPlan] Dont assign slots to VPValues with an underlying value.
This makes sure the numbering for VPValues without underlying
values is consecutive.
2024-04-09 21:30:51 +01:00
Peter Collingbourne
4ae8694cca gn build: Manually port a30662fc2acd 2024-04-09 13:24:20 -07:00
Ben Langmuir
aacb8985f7
[orc] Reduce memory usage from empty materialization info DenseMaps (#88167)
Saves several MB of memory in larger applications after linking finishes
by clearing DenseMap storage that is empty. This does not attempt to
shrink partially full materialization infos. The assumption is that
adding more after linking finishes is rare.

rdar://126145336
2024-04-09 13:01:00 -07:00
Fangrui Song
9797a7ea6b
[DWARF] Refactor findDebugNamesOffsets
Address some post-review comments in #82153 and move the function inside
llvm::dwarf, used by certain free functions.

Pull Request: https://github.com/llvm/llvm-project/pull/88064
2024-04-09 12:32:15 -07:00
Noah Goldstein
7599d478ef [InstCombine] Fold (icmp eq/ne (add nuw x, y), 0) -> (icmp eq/ne (or x, y), 0)
`(icmp eq/ne (or x, y), 0)` is probably easier to analyze than `(icmp
eq/ne x, -y)`

Proof: https://alive2.llvm.org/ce/z/2-VTb6

Closes #88088
2024-04-09 13:56:28 -05:00
Noah Goldstein
759bab0681 [InstCombine] Add tests for folding (icmp eq/ne (add nuw x, y), 0); NFC 2024-04-09 13:56:28 -05:00
Björn Pettersson
5d9d740c39
Remove the unused IntervalPartition analysis pass (#88133)
This removes the old legacy PM "intervals" analysis pass (aka
IntervalPartition). It also removes the associated Interval and
IntervalIterator help classes.

Reasons for removal:
1) The pass is not used by llvm-project (not even being tested by
   any regression tests).
2) Pass has not been ported to new pass manager, which at least
   indicates that it isn't used by the middle-end.
3) ASan reports heap-use-after-free on
      ++I;  // After the first one...
   even if false is passed to intervals_begin. Not sure if that is
   a false positive, but it makes the code a bit less trustworthy.
2024-04-09 20:12:26 +02:00
Fangrui Song
d3016aa889
[DWARF] Refactor .debug_names bucket count computation (#88087)
`getDebugNamesBucketAndHashCount` lures users to provide an array to
compute the bucket count using an O(n log n) sort. This is inefficient
as hash table based uniquifying is faster.

The performance issue matters less for Clang as the number of names is
relatively small. For `ld.lld --debug-names`, I plan to compute the
unique hash count as a side product of parallel entry pool computation,
and I just need a function to suggest a bucket count.
2024-04-09 11:02:39 -07:00
Alexey Bataev
910d2de357 [SLP]Fix PR88103: consider the sign of the compare for non-negative operands.
Need to improve detection of number of bits, required for the operand,
before doing a reduction. If the instruction is incoming operand of the
signed compare, need to consider adding an extra bit for signedness.
2024-04-09 10:47:47 -07:00
Alexey Bataev
4dfc55f7e7 [SLP][NFC]Add a test for PR88103, where zext is incoming to signed comparison. 2024-04-09 10:39:25 -07:00
Jakub Kuderski
ca705681df
Revert "[ADT] Use adl_* wrappers across STLExtras" (#88158)
Reverts llvm/llvm-project#87936

Seems like this broke some clang designated initializers tests,
reverting.
2024-04-09 13:21:16 -04:00
Jakub Kuderski
9e418c94cd
[ADT] Use adl_* wrappers across STLExtras (#87936)
Update the remaining uses of `std::begin`/`end` functions to
`adl_beging`/`end`. This is to make the behavior all the utility
functions consistent, rather than trying to fix a specific usecase.
2024-04-09 12:50:18 -04:00
Dinar Temirbulatov
528943f153
[AArch64][SME] Allow memory operations lowering to custom SME functions. (#79263)
This change allows to lower memcpy, memset, memmove to custom SME
version provided by LibRT.
2024-04-09 17:27:46 +01:00
David Green
f0e79d9152 [AArch64] Add a cost for identity shuffles.
These are mostly handled at a higher level when costing shuffles, but some
masks can end up being identity or concat masks which we can treat as free.
2024-04-09 17:16:14 +01:00
Peter Lafreniere
614a578034
[M68k] Add support for bitwise NOT instruction (#88049)
Currently the bitwise NOT instruction is not recognized. Add support for
using NOT on data registers. This is a partial implementation that puts
NOT at the same level of support as NEG currently enjoys.

Using not rather than eori cuts the length of the encoded instruction
in half or in thirds, leading to a reduction of 4-10 cycles per
instruction, on the original 68000.

This change includes tests for both bitwise and arithmetic negation.
2024-04-09 09:07:26 -07:00
Alexey Bataev
e8e67957fa [SLP]Fix PR88123: use vectorized operands consistently.
Need to use vectorized operands, not the vecop of the extractelement
instructions, to avoid false detection of the extra vector operand in
the extractelements shuffling.
2024-04-09 08:42:57 -07:00
David Green
4ac2721e51
[AArch64] Add costs for ST3 and ST4 instructions, modelled as store(shuffle). (#87934)
This tries to add some costs for the shuffle in a ST3/ST4 instruction,
which are represented in LLVM IR as store(interleaving shuffle). In
order to detect the store, it needs to add a CxtI context instruction to
check the users of the shuffle. LD3 and LD4 are added, LD2 should be a
zip1 shuffle, which will be added in another patch.

It should help fix some of the regressions from #87510.
2024-04-09 16:36:08 +01:00
Kazu Hirata
568ec1340c
[memprof] Use structured binding (NFC) (#88096) 2024-04-09 08:25:41 -07:00
Sam Tebbs
fb8dbd1fb6
[AArch64] Remove copy in SVE/SME predicate spill and fill (#81716)
7dc20ab introduced an extra COPY when spilling and filling a PNR
register, which can't be elided as the input (PNR predicate) and output
(PPR predicate) register classes differ. The patch adds a new register
class that covers both PPR and PNR so that STR_PXI and LDR_PXI can
take either of them, removing the need for the copy.
2024-04-09 16:17:27 +01:00
Simon Pilgrim
3bfd5c6424
[TTI] getCommonMaskedMemoryOpCost - consistently use getScalarizationOverhead instead of ExtractElement costs for address/mask extraction. (#87771)
These aren't unknown extraction indices, we will be extracting every address/mask element in sequence.
2024-04-09 15:42:51 +01:00
Philip Reames
e47fd09f8e
[RISCV] Use shNadd for scalable stack offsets (#88062)
If we need to multiply VLENB by 2, 4, or 8 and add it to the stack
pointer, we can do so with a shNadd instead of separate shift and add
instructions.
2024-04-09 07:29:10 -07:00
Vyacheslav Levytskyy
23b058cb7f
[SPIR-V] Re-implement switch and improve validation of forward calls (#87823)
This PR fixes issue https://github.com/llvm/llvm-project/issues/87763
and preserves valid CFG in cases when previous scheme failed to generate
valid code for a switch statement. The PR hardens one existing test case
and adds one more test case as a validation of a new switch generation.
Tests are passing spirv-val now.

This PR also improves validation of forward calls.
2024-04-09 16:15:44 +02:00
Natalie Chouinard
1e44d9ac5e
[SPIR-V] Map llvm.{min,max}num to GL::N{Min,Max} (#88009)
SPIR-V intsruction selection was mapping the LLVM float min/max
intrinsics to FMin and FMax respectively for GL/Vulkan environments,
which does not match the intrinsics' documented treatment of NaN
operands. This patch switches the mapping to the correctly matched NMin
and NMax operations.

Fixes #87072
2024-04-09 09:41:47 -04:00
Simon Pilgrim
961d91abd3 [X86] shuffle-vs-trunc-128.ll - add common AVX2 check prefix 2024-04-09 14:14:01 +01:00
Simon Pilgrim
a4cf479cdf [X86] shuffle-vs-trunc-128.ll - add BWVL-ONLY/VBMI/VBMI-FAST/VBMI-SLOW check prefixes to recover missing test checks
It is VERY annoying that update_llc_test_checks.py silently fails instead of correctly warning when this happens :(
2024-04-09 13:44:01 +01:00
Simon Pilgrim
866a1bc814 [X86] Add test coverage for #88030 2024-04-09 13:23:44 +01:00
Simon Pilgrim
4023329bbf [X86] collectConcatOps - add ability to recurse through insert_subvector chains
Allows us to match insert_subvector(insert_subvector(undef, insert_subvector(insert_subvector(undef, x, 0), y, 1), 0), 0),
                                    insert_subvector(insert_subvector(undef, z, 0), w, 1), 2)
2024-04-09 13:23:44 +01:00
Paul Walker
8795822f6a
[NFC][LLVM][CodeGen] Refactor SVE unpredicated binop isel patterns. (#84045)
Create PatFrags for fadd, fmul, fsub, mul, smulh and umulh so that a
single set of patterns can be used. Patch then removes unused classes
and some redundant whitespace.
2024-04-09 12:19:53 +01:00
Florian Hahn
c836983671
[VPlan] Remove unused first mask op from VPBlendRecipe. (#87770)
VPBlendRecipe does not use the first mask operand. Removing it allows
VPlan-based DCE to remove unused mask computations.

This also fixes #87410, where unused Not VPInstructions are considered
having only their first lane demanded, but some of their operands
providing a vector value due to other users.

Fixes https://github.com/llvm/llvm-project/issues/87410

PR: https://github.com/llvm/llvm-project/pull/87770
2024-04-09 11:14:05 +01:00