267048 Commits

Author SHA1 Message Date
Matt Arsenault
0832b85e0f ValueTracking: Add baseline tests for vector fpclass handling 2024-04-08 09:26:12 -04:00
Nathan Sidwell
f6357bb428
[llvm][docs] Resort cmake macros (#87551)
The cmake macro documentation had once again become unsorted. For names
of the form 'PREFIX_{list-or-category}_SUFFIX' I collate as 'PREFIX_SUFFIX'.
2024-04-08 09:02:10 -04:00
paperchalice
eb07600f8e
[NewPM] support disablePass, insertPass in CodeGenPassBuilder (#87147)
Currently only machine function passes support `insertPass`, but it
seems to be enough, all targets tune their pipelines when adding machine
function passes.
2024-04-08 20:52:37 +08:00
Matt Arsenault
95f984f37e ValueTracking: Don't use unnecessary null checked dyn_cast 2024-04-08 08:32:04 -04:00
Matt Arsenault
8cb642bf18 GlobalISel: Regenerate test checks 2024-04-08 08:32:04 -04:00
Malay Sanghi
38f996bb2b
Replace copy with a reference. (#87975) 2024-04-08 20:31:51 +08:00
Matt Arsenault
fc9a5076c3 llvm-reduce: Reduce nuw/nsw flags from trunc 2024-04-08 08:17:09 -04:00
Matt Arsenault
acb2a47576 AMDGPU: Regenerate test checks 2024-04-08 08:17:09 -04:00
Luke Lau
8b3b4a92ad
[RISCV] Fix canFoldToVWWithSameExtension allowing different FP extensions (#87978) 2024-04-08 19:20:36 +08:00
Simon Pilgrim
170c525d79 [X86] combineExtractVectorElt - fold extract(trunc(x),c) -> trunc(extract(x,c)) 2024-04-08 11:01:19 +01:00
Zentrik
cf7d36fe34
[NFC] Fix misspellings of effects (#87795) 2024-04-08 11:18:59 +02:00
Pengcheng Wang
364028a1a5
[RISCV] Zimop/Zcmop are ratified
Remove them from experimental.

See also:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc

Reviewers: kito-cheng

Reviewed By: kito-cheng

Pull Request: https://github.com/llvm/llvm-project/pull/87966
2024-04-08 16:40:02 +08:00
David Green
0bfea40101 [AArch64] More shuffle-store test cases. NFC 2024-04-08 09:19:47 +01:00
David Green
9fd2e2c2fd
[DAG][AArch64] Support masked loads/stores with nontemporal flags (#87608)
SVE has some non-temporal masked loads and stores. The metadata coming
from the nodes is not copied to the MMO at the moment though, meaning it
will generate a normal instruction. This patch ensures that the right
flags are set if the instruction has non-temporal metadata.
2024-04-08 08:53:27 +01:00
David Green
ac321cbb03
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
This attempts to standardize and extend some of the insert vector
element lowering. Most notably:
- More types are handled by splitting illegal vectors.
- The index type for G_INSERT_VECTOR_ELT is canonicalized to
  TLI.getVectorIdxTy(), similar to extact_vector_element.
- Some of the existing patterns now have the index type specified to
  make sure they can apply to GISel too.
- The C++ selection code has been removed, relying on tablegen patterns.
- G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to
  use a i32 type, allowing the existing patterns to apply.
- Variable index inserts are lowered in post-legalizer lowering,
  expanding into a stack store and reload.
2024-04-08 08:44:13 +01:00
Bevin Hansson
110c22fe12
[ExpandLargeFpConvert] Support bfloat. (#87619)
The conversion expansions did not properly handle bfloat types.

I'm not certain that these expansions are completely correct;
I don't have any experience with AMDGPU or the ability to run
anything to test it.

Note that it doesn't seem like AMDGPU with GlobalISel can
handle fptrunc of float to bfloat, which is needed for itofp.
I've omitted the GISEL run for the bfloat case.

This fixes #85379.
2024-04-08 09:07:55 +02:00
Lang Hames
fdd023612c Revert "[ORC] Replace some KV loop variables with structured bindings."
This reverts commit 006aaf32258fc27656c936f6aad729e4c77e3847 while I
investigate some bot failures (See e.g.
https://lab.llvm.org/buildbot/#/builders/109/builds/86659).
2024-04-08 00:02:01 -06:00
Pengcheng Wang
73ddb2a747
[RISCV] Store VLMul/NF into RegisterClass's TSFlags
This TSFlags was introduced by https://reviews.llvm.org/D108767.

A base class of all RISCV RegisterClass is added and we store
IsVRegClass/VLMul/NF into TSFlags and add helpers to get them.

This can reduce some lines and I think there will be more usages.

Reviewers: preames, topperc

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/84894
2024-04-08 13:35:37 +08:00
Nikita Popov
91189afef5 Revert "[indvars] Missing variables at Og: (#69920)"
This reverts commit 739fa1c84b92b8af7dceedf2e5ad808a64e85a57.

This introduces a layering violation by using IR in Support headers.
2024-04-08 14:31:52 +09:00
Lang Hames
006aaf3225 [ORC] Replace some KV loop variables with structured bindings.
This allows us to remove a lot of boilerplate .first and .second references
and improve readability.

Coding my way home: 1.58814S, 91.93889W
2024-04-07 23:30:46 -06:00
Pengcheng Wang
f3b5597364
[RISCV] Use larger copies when register tuples are aligned
When the encoding of register tuples are aligned, we can use a copy
with larger LMUL to reduce copies.

Reviewers: preames, topperc, lukel97

Reviewed By: topperc, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/84455
2024-04-08 13:24:57 +08:00
Carlos Alberto Enciso
739fa1c84b
[indvars] Missing variables at Og: (#69920)
https://bugs.llvm.org/show_bug.cgi?id=51735
https://github.com/llvm/llvm-project/issues/51077

In the given test case:
 ```
4 ...
 5 void bar() {
 6   int End = 777;
 7   int Index = 27;
 8   char Var = 1;
 9   for (; Index < End; ++Index)
10     ;
11   nop(Index);
12 }
13 ...
```
Missing local variable `Index` after loop `Induction Variable Elimination`. When adding a breakpoint at line `11`, LLDB does not have information on the variable. But it has info on `Var` and `End`.
2024-04-08 05:31:56 +01:00
Haohai Wen
cebf77fb93
[CodeGen][DebugInfo] Add missing DebugLoc for SplitCriticalEdge (#72192)
In SplitCriticalEdge, DebugLoc of the branch instruction in new created
MBB was set to empty. It should be set and we can find proper DebugLoc
for it in most cases. This patch set it to non empty merged DebugLoc of
current MBB branches.
2024-04-08 09:44:34 +08:00
Philip Reames
da675b922c [RISCV] Expand test coverage of stack offsets between 2^11 and 2^15
Adds two sets of tests.  First, one for prolog/epilogue insertions where
the second stack adjustment can be done with shNadd for zba.  Second, a
set of tests with offsets off SP in the same ranges, but also adding
varying alignments.
2024-04-07 15:22:25 -07:00
Kazu Hirata
4d1bb7699b
[memprof] Fix a typo in writeMemProfV1 (#87890)
This patch borrows memprof-merge.test to test --memprof-version.
2024-04-07 15:06:13 -07:00
Lang Hames
649523f6f7 [ORC] Add an ExecutionSession state verifier.
Add an ExecutionSession state verifier, enabled under EXPENSIVE_CHECKS, that can
be used to identify inconsistent session state to assist in tracking down bugs.

This initial version was motivated by investigation of the EDU-update bug that
was fixed in a671ceec334.

rdar://125376708
2024-04-07 15:36:45 -06:00
Florian Hahn
15d11a4de9
[VPlan] Track IsOrdered in VPReductionRecipe, remove use of ILV (NFCI).
Instead of using ILV.useOrderedReductions during ::execute, instead
store the information at recipe construction.

Another step towards making recipe'::execute independent of legacy ILV.
2024-04-07 20:33:22 +01:00
Kazu Hirata
3f16ff4e68
[memprof] Use static instead of anonymous namespaces (#87889)
This patch replaces anonymous namespaces with static as per LLVM
Coding Standards.
2024-04-07 11:38:15 -07:00
Cyndy Ishida
a3bb9c2b06
[cmake] Prevent implicitly passing -no_exported_symbols (#87846)
* It is possible to setup llvm-project builds without going through
`llvm/CMakeList.txt` so the fatal error handling should be smarter.
* Disable option on Apple style lldb-linux builds.
2024-04-07 10:22:34 -07:00
David Green
d57d094779 [AArch64] Add test for LD2/LD3/LD4 shuffle cost models. NFC 2024-04-07 18:18:32 +01:00
Alexey Bataev
a612524197
[SLP]Fix the cost of the reduction result to the final type.
Need to fix the way the cost is calculated, otherwise wrong cast opcode
can be selected and lead to the over-optimistic vector cost. Plus, need
to take into account reduction type size.

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/87528
2024-04-07 09:51:47 -04:00
Jacob Lifshay
da5a86b53e
[IR] Fix typo in trunc nuw semantics; NFC (#87285) 2024-04-07 15:54:10 +08:00
David Green
869797daca [VectorCombine] Add a debug message for foldShuffleOfCastop. NFC
This optimization, much like the existing foldShuffleOfBinops can cause a
lot of regressions. Add a quick debug message to make the costs are more
obvious.
2024-04-07 07:54:22 +01:00
Jianjian Guan
bc8726b16b
[RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318)
vfmv, vfmerge should support bfloat vector when we have both Zvfbfmin
and Zfbfmin, this patch tries to support vfmv first.
2024-04-07 10:41:47 +08:00
NAKAMURA Takumi
d08a76d1ac Fix warnings discovered by #87348 [-Wunused-but-set-variable] 2024-04-07 11:02:08 +09:00
AtariDreams
8389b3bf60
[X86] Fix typo: QWORD alignment is greater than or equal to 8, not greater than 8 (#87819)
Align(8) is QWORD aligned, but this was checking to see if alignment was
greater than that, when it should have been checking for being greater
than OR EQUAL to Align(8).

This bug was introduced in
https://github.com/llvm/llvm-project/commit/6a6af30d433d7 during the
transition to the Align type.
2024-04-07 08:43:13 +08:00
Noah Goldstein
e4db938a4e [ValueTracking] Support non-constant idx for computeKnownFPClass of insertelement
Its same logic as before, we just need to intersect what we know about
the new Elt and the entire pre-existing Vec.

Closes #87708
2024-04-06 17:51:15 -05:00
Noah Goldstein
d5b48ceb74 [ValueTracking] Add tests for non-constant idx for fpclass of insertelement; NFC 2024-04-06 17:51:15 -05:00
darkbuck
8e98435ae9
[GISel][Combine] Enhance combining on G_BUILD_VECTOR
Reviewers: aemerson, arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/87831
2024-04-06 18:33:01 -04:00
Martin Storsjö
bd9486b4ec Revert "[SLP]Improve minbitwidth analysis for abs/smin/smax/umin/umax intrinsics."
This reverts commit 66b528078e4852412769375e35d2a672bf36a0ec.

This commit caused miscompilations, breaking tests in the libyuv
testsuite - see
https://github.com/llvm/llvm-project/pull/86135#issuecomment-2041049709
for more details.
2024-04-06 23:53:26 +03:00
Sizov Nikita
d38bff460a
[AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (#76644)
Fold BICi if all destination bits are already known to be zeroes

```llvm
define <8 x i16> @haddu_known(<8 x i8> %a0, <8 x i8> %a1) {
  %x0 = zext <8 x i8> %a0 to <8 x i16>
  %x1 = zext <8 x i8> %a1 to <8 x i16>
  %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
  %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
  ret <8 x i16> %res
}
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
```

```
haddu_known:                            // @haddu_known
        ushll   v0.8h, v0.8b, #0
        ushll   v1.8h, v1.8b, #0
        uhadd   v0.8h, v0.8h, v1.8h
        bic     v0.8h, #254, lsl #8 <-- this one will be removed as we know high bits are zero extended
        ret
```

Fixes #53881
Fixes #53622
2024-04-06 21:41:24 +01:00
Matt Arsenault
4cb110a84f
[RFC] IR: Support atomicrmw FP ops with vector types (#86796)
Allow using atomicrmw fadd, fsub, fmin, and fmax with vectors of
floating-point type. AMDGPU supports atomic fadd for <2 x half> and <2 x
bfloat> on some targets and address spaces.

Note this only supports the proper floating-point operations; float
vector typed xchg is still not supported. cmpxchg still only supports
integers, so this inserts bitcasts for the loop expansion.

I have support for fp vector typed xchg, and vector of int/ptr
separately implemented but I don't have an immediate need for those
beyond feature consistency.
2024-04-06 15:27:45 -04:00
Florian Hahn
fa8a726672
[LV] Make global_alias.ll test independent of O1 pipeline.
Update global_alias.ll with the IR after the O1 pipeline. Depending on
the O1 makes the tests more fragile and also makes it more difficult to
reason about the behavior of the tests, as it doesn't show the IR before
LoopVectorize.
2024-04-06 14:48:41 +01:00
Florian Hahn
233c030dcb
[LV] Add extra tests for induction cost modeling. 2024-04-06 12:36:07 +01:00
Ramkumar Ramachandra
0e8b61f8e0
llvm-objdump/ELF: fix crash when reading dyn str table (#87519)
When reading the dynamic string table, llvm-objdump used to crash if the
ELF was malformed, due to an erroneous consumption of error status.
Instead, propogate the error status to the caller, fixing the crash, and
printing a warning.
2024-04-06 12:22:24 +01:00
Jakub Kuderski
c8f3d211fc
[ADT] Allow reverse to find free rbegin/rend functions (#87840)
Lift the requirement that rbegin/rend must be member functions. Also
allow the rbegin/rend to be found through Argument Dependent Lookup
(ADL) and add `adl_rbegin`/`adl_rend` to STLExtras.
2024-04-05 22:40:18 -04:00
Craig Topper
8bd391457f
[RISCV] Rename OP-P to OP-VE. (#87546)
This has been updated in the isa-manual
https://github.com/riscv/riscv-isa-manual/pull/1311
2024-04-05 17:02:03 -07:00
Cyndy Ishida
fe45029dbd [cmake] Back out of making unsupported -no_exported_symbols linker a
fatal error for now

Appeases build bots while being investigated.
2024-04-05 14:50:19 -07:00
Cyndy Ishida
25cf27910c
[cmake] Build executables with -no_exported_symbols when building Apple toolchain (#87684)
Building the Apple way turns off plugin support, meaning we don't need
to export unloadable symbols from all executables. While deadstripping
effects aren't expected to change, enabling this across all tools
prevents the creation of export tries. This saves us ~3.5 MB in just the
universal build of `clang`.
2024-04-05 14:41:20 -07:00
Amara Emerson
60fc4ac67a [GlobalISel] Don't form anyextending atomic loads.
Until we can reliably check the legality and improve our selection of these,
don't form them at all.
2024-04-05 13:34:59 -07:00