495344 Commits

Author SHA1 Message Date
Martin Storsjö
336bdf1a25 [verify-uselistorder] Fix a typo, fix linking
This fixes a typo from 2ef612050844355906e4b67d892a00bbb58c41d6,
which broke the build with errors like:

    ld.lld: error: undefined symbol: LoadBitcodeIntoNewDbgInforFormat
    >>> referenced by verify-uselistorder.cpp
    >>>               tools/verify-uselistorder/CMakeFiles/verify-uselistorder.dir/verify-uselistorder.cpp.o:(main)
    >>> did you mean: LoadBitcodeIntoNewDbgInfoFormat
    >>> defined in: lib/libLLVMBitReader.a(BitcodeReader.cpp.o)
    collect2: error: ld returned 1 exit status
2024-03-25 11:53:20 +02:00
pvanhout
7434a6b96c [TableGen] Fix Linker Errors
Fix linker errors after landing fa3d789df15bd1f58fb8ba4ea3be909218cf7f03
2024-03-25 10:50:08 +01:00
Alexandros Lamprineas
772e316457
[FMV] Allow multi versioning without default declaration. (#85454)
This was a limitation which has now been lifted. Please read the
thread below for more details:

https://github.com/llvm/llvm-project/pull/84405#discussion_r1525583647

Basically it allows to separate versioned implementations across
different TUs without having to share private header files which
contain the default declaration.

The ACLE spec has been updated accordingly to make this explicit:
"Each version declaration should be visible at the translation
 unit in which the corresponding function version resides."

https://github.com/ARM-software/acle/pull/310

If a resolver is required (because there is a caller in the TU),
then a default declaration is implicitly generated.
2024-03-25 09:43:41 +00:00
Orlando Cazalet-Hyams
8263a88334
[RemoveDIs] Load into new debug info format by default in llvm-link (#86274)
Directly load all bitcode into the new debug info format in llvm-link.
This means that new-mode bitcode no longer round-trips back to old-mode
after parsing, and that old-mode bitcode gets auto-upgraded to new-mode
debug info (which is the current in-memory default in LLVM).
2024-03-25 09:29:19 +00:00
Orlando Cazalet-Hyams
2ef6120508
[RemoveDIs] Do not load into new debug info format from bitcode by default (#86268)
This is NFC right now, as the global default behaviour is also "do not
load into the new debug info format by default", but we want to change
that soon.

Additionally unconditionally convert from the new debug info format into
if we've loaded into it (e.g., if the bitcode file loaded was already in
the new format).

The latter change is needed because verify-uselistorder doesn't yet
understand DbgRecords (it doesn't know how to map them).

The former change is needed because if we load from an old debug format
bitcode file but load directly into the new format _and then convert
back to the old mode after_, the use-lists of the debug intrinsic
functions (the functions' global value uses) change.
2024-03-25 09:28:01 +00:00
Orlando Cazalet-Hyams
e550022b68
[RemoveDIs] Load into new debug info format by default in llvm-dis (#86276)
Directly load all bitcode into the new debug info format in llvm-dis.
This means that new-mode bitcode no longer round-trips back to old-mode
after parsing, and that old-mode bitcode gets auto-upgraded to new-mode
debug info (which is the current in-memory default in LLVM).
2024-03-25 09:26:27 +00:00
Shih-Po Hung
3cb024198f
[RISCV][CostModel] Estimate cost of llvm.vector.reduce.fmaximum/fminimum (#80697)
The ‘llvm.vector.reduce.fmaximum/fminimum.*’ intrinsics propagate NaNs
if any element of the vector is a NaN.
Following #79402, the patch adds the cost for NaN check (vmfne + vcpop)
2024-03-25 17:17:36 +08:00
Orlando Cazalet-Hyams
cbbbab349e [RemoveDIs] Enable direct-to-bitcode writing by default
Follow on from #83251. This patch simply enables the behaviour by default in
order to provide an easily revertible capstone.
2024-03-25 09:15:41 +00:00
Vyacheslav Levytskyy
b0d03ccc08
[SPIR-V] Fix illegal OpConstantComposite instruction with non-const constituents in SPIR-V Backend (#86352)
This PR fixes illegal use of OpConstantComposite with non-constant
constituents. The test attached to the PR is able now to satisfy
`spirv-val` check. Before the fix SPIR-V Backend produced for the
attached test case a pattern like
```
%a = OpVariable %_ptr_CrossWorkgroup_uint CrossWorkgroup %uint_123
%11 = OpConstantComposite %_struct_6 %a %a
```
so that `spirv-val` complained with
```
error: line 25: OpConstantComposite Constituent <id> '10[%a]' is not a constant or undef.
  %11 = OpConstantComposite %_struct_6 %a %a
```
2024-03-25 10:14:46 +01:00
Vyacheslav Levytskyy
1d250d9099
[SPIR-V] Improve type inference in SPIR-V Backend for opaque pointers (#86283)
This PR improves type inference in SPIR-V Backend for opaque pointers,
accounting or a case when there is a chain of function calls that allows
to deduce formal parameter types from actual arguments. The attached
test demonstrates the case.
2024-03-25 10:14:08 +01:00
Vyacheslav Levytskyy
99c40f6ba6
[SPIR-V] Introduce a command line option to support compatibility with Khronos SPIRV Translator (#86101)
SPIRV-LLVM-Translator project
(https://github.com/KhronosGroup/SPIRV-LLVM-Translator) from Khronos
Group is a tool and a library for bi-directional translation between
SPIR-V and LLVM IR. In its backward translation from SPIR-V to LLVM IR
SPIRV-LLVM-Translator isn't necessarily able to cover the same SPIR-V
patterns/instructions set that SPIRV Backend produces, even if we target
the same SPIR-V version in both SPIRV-LLVM-Translator and SPIRV Backend
projects.

To improve interoperability and ability to apply SPIRV Backend output in
different products this PR introduces a notion of a mode of SPIR-V
output that is compatible with a subset of SPIR-V supported by
SPIRV-LLVM-Translator. This includes a new command line option that
doesn't influence default behavior of SPIRV Backend and one test case
that demonstrates how this command line option may be used to get a
practical benefit of producing that one of two possible and similar
output options that can be understood by SPIRV-LLVM-Translator.
2024-03-25 10:13:42 +01:00
David Stuttard
75e528fdd9
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
buffer_load instructions that use TFE also need to zero initialize
return values similar to how the image instructions currently work. Add
support for this with standard zero init of all results + zero init of
just TFE flag when enable-prt-strict-null subtarget feature is disabled.
2024-03-25 09:01:46 +00:00
Stefan Gränitz
0cf4788d9d
[clang-repl] Factor out CreateJITBuilder() and allow specialization in derived classes (#84461)
The LLJITBuilder interface provides a very convenient way to configure
the ORCv2 JIT engine. IncrementalExecutor already used it internally to
construct the JIT, but didn't provide external access. This patch lifts
control of the creation process to the Interpreter and allows injection
of a custom instance through the extended interface. The Interpreter's
default behavior remains unchanged and the IncrementalExecutor remains
an implementation detail.
2024-03-25 09:44:25 +01:00
Stefan Gränitz
aa962d67ee
[clang-repl] Fix Value for platforms where unqualified char is unsigned (#86118)
Signedness of unqualified `char` is unspecified and varies between
platforms. This patch adds `Char_U` in `REPL_BUILTIN_TYPES` to account
for platforms that default to `unsigned char`.
2024-03-25 09:42:41 +01:00
Pierre van Houtryve
fa3d789df1
[RFC][TableGen] Restructure TableGen Source (#80847)
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)

Fixes #80647
2024-03-25 09:40:35 +01:00
Pierre van Houtryve
babbdad15b
[AMDGPU] Handle non-register operands for S_SUB/ADD_U64_PSEUDO (#86104)
This pseudo uses SSrc_b64 so it allows both an immediate or a register,
but the lowering crashed on immediate operands.
2024-03-25 09:23:40 +01:00
Luke Lau
373e77b4c0
[RISCV] Generalize (sub zext, zext) -> (sext (sub zext, zext)) to add (#86248)
This generalizes the combine added in #82455 to other binary ops,
beginning with adds in this patch.

Because the two zext operands are always +ve when treated as signed, and
we don't get any overflow since the add is carried out in at least N * 2
bits of the narrow type, the result of the add will always be +ve. So we
can use a zext for the outer extend, unlike sub which may produce a -ve
result from two +ve operands.

Although we could still use sext for add, I plan to add support for
other binary ops like mul in a later patch, but mul requires zext to be
correct (because the maximum value will take up the full N * 2 bits). So
I've opted to use zext here too for consistency.

Alive2 proof: https://alive2.llvm.org/ce/z/PRNsUM
2024-03-25 13:08:56 +08:00
Wang Pengcheng
d9746a6a5d
[RISCV][NFC] Pass LMUL to copyPhysRegVector
The opcode will be determined by LMUL.

Reviewers: preames, lukel97, topperc

Reviewed By: lukel97, topperc

Pull Request: https://github.com/llvm/llvm-project/pull/84448
2024-03-25 12:42:59 +08:00
Wang Pengcheng
6af6416e89
[RISCV] Add a tune feature to disable stripping W suffix (#86255)
We have a hidden option to disable it, but I'd like to make it a
tune feature.

For some implementations, instructions with W suffix would be less
costly as they only perform on 32 bits data. Though we may lose some
chances to compress.
2024-03-25 11:44:16 +08:00
Sergei Barannikov
5e5b656102
[MC] Make MCParsedAsmOperand::getReg() return MCRegister (#86444) 2024-03-25 05:13:48 +03:00
Phoebe Wang
2e4e04c590
[X86][BF16] Do not lower to VCVTNEPS2BF16 without AVX512VL (#86395)
Fixes: #86305
2024-03-25 10:06:12 +08:00
Kai Sasaki
7d2d8e2a72
[mlir][complex] Fastmath flag for the trigonometric ops in complex (#85563)
Support Fastmath flag to convert trigonometric ops in the complex
dialect.

See:
https://discourse.llvm.org/t/rfc-fastmath-flags-support-in-complex-dialect/71981
2024-03-25 10:59:42 +09:00
Finn Plummer
230b1895c4
[mlir][spirv] Add folding for [S|U|LessThan[Equal] (#85435)
Add missing constant propogation folder for [S|U]LessThan[Equal].

Implement additional folding when the operands are equal for all ops.

Allows for constant folding in the IndexToSPIRV pass.

Part of work #70704
2024-03-24 18:56:47 -07:00
Owen Pan
cceedc939a
[clang-format] Fix a crash with AlignArrayOfStructures option (#86420)
Fixes #86109.
2024-03-24 15:22:40 -07:00
Min Hsu
67f2267ae0 [M68k][NFC] Suppress warning on an unused variable when assertion is disabled
NFC.
2024-03-24 14:24:44 -07:00
Fangrui Song
18a49f03aa [ELF] Merge relaIplt into relaDyn
`relaIplt` was added so that IRELATIVE relocations are placed at the end
of .rela.dyn (since https://reviews.llvm.org/D65651) or .rela.plt
(--pack-dyn-relocs=android[+relr]). Unfortunately, handling `relaIplt`
requires special cases all over the code base. We can extend
partitionRels/computeRels to partition both RELATIVE and IRELATIVE
relocations, rendering `relaIplt` unneeded.

The change allows IRELATIVE relocations in the DT_ANDROID_REL[A] table
(untested?!), which may be processed before other types of relocations.
This seems acceptable for Bionic's DEFINE_IFUNC_FOR use cases.

In addition, this change simplies changing .rel[a].dyn to a compact
relocation format (CREL).

SHF_INFO_LINK is removed from .rel[a].dyn with IRELATIVE relocations.
(See https://reviews.llvm.org/D89828).
2024-03-24 14:07:09 -07:00
Florian Hahn
f0a8738401
[VPlan] Generate CalculateTripCountMinusVF for Part 0 only. (NFCI).
The value produced by CalculateTripCountMinusVF VPInstructions is
independent of the part. Only compute it for part 0 and use that for
other parts.
2024-03-24 20:59:54 +00:00
Hui
81e2693c12
[libc++][test] Fix race condition in condition_variable_any tests (#84788)
Some tests in `condition_variable_any` use two `shared_lock` to guard,
which does not work.
The fix is to make the writer to use `unique_lock`
2024-03-24 20:52:47 +00:00
Joseph Huber
9f0321ccf1 [Libomptarget] Make plugins depend explicitly on intrinsics_gen
Summary:
It's possible for the OpenMP offloading plugins to be build before
tablegen is run despite the fact that we rely on it. Simply make it
depend on it currently.
2024-03-24 15:24:35 -05:00
Lang Hames
488a18738f [JITLink][ELF] Improve ELF section start/end symbol handling.
This commit adds section start and stop symbol handling to ELF/aarch64, and
fixes the section symbol prefixes (using `__start_` and `__stop_`, rather than
`__start` and `__end`). It also adds a testcase for handling of these symbols.
2024-03-24 14:54:15 -05:00
Joseph Huber
909ea28ac6 [Libomptarget] Specificall add LLVM include dirs in plugins 2024-03-24 14:29:39 -05:00
Piotr Zegar
d4a4585165
[clang-tidy] Ignore expresions in unevaluated context in bugprone-inc-dec-in-conditions (#85849)
Skip checking for references to variable in unevaluated context, like
decltype, static_assert and so on.

Closes #85838
2024-03-24 19:52:19 +01:00
Arthur Eubanks
4804805132
[lld/ELF][X86] Respect outSecOff when checking if GOTPCREL can be relaxed (#86334)
The existing implementation didn't handle when the input text section
was some offset from the output section.

This resulted in an assert in relaxGot() with an lld built with asserts
for some large binaries, or even worse, a silently broken binary with an
lld without asserts.
2024-03-24 11:43:15 -06:00
houndlord
9632e1515c
Match fixed width ISD::AVGFLOORS + ISD::AVGCEILS patterns (#86222) 2024-03-24 15:33:16 +00:00
Marc Auberer
b3fe27f2be
[InstCombine] Copy flags of extractelement for extelt -> icmp combine (#86366)
Fixes #86164
2024-03-24 16:14:56 +01:00
David Green
e8d5223ce4 [AArch64] Additional GISel test coverage. NFC 2024-03-24 12:32:47 +00:00
Simon Pilgrim
6c6fe4b2ae [X86] known-never-zero.ll - add 32-bit test coverage
Enabled vector coverage as well: i686+SSE2 and x64_64+AVX

Should improve test quality for #85722
2024-03-24 11:33:51 +00:00
AtariDreams
4d69855e9d
[flang] Silence MSVC warning about shifts (NFC) (#83737)
Yes, 64-bit shifts are intended.
2024-03-24 10:48:04 +00:00
Vitaly Buka
4acd84e7cc
Revert "[compiler-rt] Also consider SIGPROF as a synchronous signal" (#86416)
Reverting #85188 with follow up patches.

This reverts commit 362d26366d0175f01ffb6085eb747a6e40f01147.
This reverts commit c9bdeabdf4b46fbf1f6a9fcbf9cd61d460b18c08.
This reverts commit 6bc6e1ace9fa8453e164fa04b5d9acd5a77e089a.
This reverts commit 01fa550ff654d6724e6da54c877032baeddff14b.
This reverts commit ddcbab37ac0e5743a8d39be3dd48d967f4c85504.
2024-03-24 01:22:48 -07:00
yingopq
5d7fd6a04a
[Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902)
Fix #61881
2024-03-24 02:35:42 -04:00
Matthias Springer
a45e58af1b
[mlir][bufferization] Add BufferViewFlowOpInterface (#78718)
This commit adds the `BufferViewFlowOpInterface` to the bufferization
dialect. This interface can be implemented by ops that operate on
buffers to indicate that a buffer op result and/or region entry block
argument may be the same buffer as a buffer operand (or a view thereof).
This interface is queried by the `BufferViewFlowAnalysis`.

The new interface has two interface methods:
* `populateDependencies`: Implementations use the provided callback to
declare dependencies between operands and op results/region entry block
arguments. E.g., for `%r = arith.select %c, %m1, %m2 : memref<5xf32>`,
the interface implementation should declare two dependencies: %m1 -> %r
and %m2 -> %r.
* `mayBeTerminalBuffer`: An SSA value is a terminal buffer if the buffer
view flow analysis stops at the specified value. E.g., because the value
is a newly allocated buffer or because no further information is
available about the origin of the buffer.

Ops that implement the `RegionBranchOpInterface` or `BranchOpInterface`
do not have to implement the `BufferViewFlowOpInterface`. The buffer
dependencies can be inferred from those two interfaces.

This commit makes the `BufferViewFlowAnalysis` more accurate. For
unknown ops, it conservatively used to declare all combinations of
operands and op results/region entry block arguments as dependencies
(false positives). This is no longer the case. While the analysis is
still a "maybe" analysis with false positives (e.g., when analyzing ops
such as `arith.select` or `scf.if` where the taken branch is not known
at compile time), results and region entry block arguments of unknown
ops are now marked as terminal buffers.

This commit addresses a TODO in `BufferViewFlowAnalysis.cpp`:
```
// TODO: We should have an op interface instead of a hard-coded list of
// interfaces/ops.
```
It is no longer needed to hard-code ops.
2024-03-24 12:48:19 +09:00
Kazu Hirata
74799f4240
[memprof] Add call stack IDs to IndexedAllocationInfo (#85888)
The indexed MemProf file has a huge amount of redundancy.  In a large
internal application, 82% of call stacks, stored in
IndexedAllocationInfo::CallStack, are duplicates.

We should work toward deduplicating call stacks by referring to them
with unique IDs with actual call stacks stored in a separate data
structure, much like we refer to memprof::Frame with memprof::FrameId.

At the same time, we need to facilitate a graceful transition from the
current version of the MemProf format to the next.  We should be able
to read (but not write) the current version of the MemProf file even
after we move onto the next one.

With those goals in mind, I propose to have an integer ID next to
CallStack in IndexedAllocationInfo to refer to a call stack in a
succinct manner.  We'll gradually increase the areas of the compiler
where IDs and call stacks have one-to-one correspondence and
eventually remove the existing CallStack field.

This patch adds call stack ID, named CSId, to IndexedAllocationInfo
and teaches the raw profile reader to compute unique call stack IDs
and store them in the new field.  It does not introduce any user of
the call stack IDs yet, except in verifyFunctionProfileData.
2024-03-23 19:50:15 -07:00
Owen Anderson
7c9b5228da
Only check assertions that were meant to apply to the normal case of non-splat vector SREM expansion when we aren't hitting the special case. (#86238)
Fixes https://github.com/llvm/llvm-project/issues/84830
Introduced in https://github.com/llvm/llvm-project/pull/82706
2024-03-23 21:49:29 -05:00
Amir Ayupov
d7d2f7ca62
[BOLT] Emit intra-function control flow in YAMLBAT
Attach branch counters to YAML profile, covering intra-function control
flow.

Depends on: https://github.com/llvm/llvm-project/pull/86353

Test Plan: Updated bolt/test/X86/bolt-address-translation-yaml.test

Reviewers: rafaelauler, dcci, ayermolo, maksfb

Reviewed By: rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/76911
2024-03-23 19:11:49 -07:00
LLVM GN Syncbot
8e698a1d8e [gn build] Port b68e2eba0bc8 2024-03-24 00:56:59 +00:00
Nico Weber
a118769ec8 [gn] port 3bc71c2abf 2024-03-23 20:56:45 -04:00
Felix (Ting Wang)
90a7fc366a
[PowerPC][NFC] Add base test case for small-local-dynamic-tls on AIX (#84711) 2024-03-24 08:46:45 +08:00
Amir Ayupov
a91cd53de3
[BOLT][NFC] Refactor BAT metadata data structures
Hide the implementations of `FuncHashes` and `BBHashMap` classes,
getting rid of `at` accessors that could throw an exception.

Test Plan: NFC

Reviewers: ayermolo, maksfb, dcci, rafaelauler

Reviewed By: rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/86353
2024-03-23 16:08:31 -07:00
Michał Górny
e14c6fa31a
[clang] [cmake] Add cmake module dir before using GetDarwinLinkerVersion (#86386)
Move the code adding top-level cmake/Modules directory to
CMAKE_MODULE_PATH prior to including `GetDarwinLinkerVersion`, in order
to fix standalone builds.

Fixes a regression introduced by
3bc71c2abfa00413fd15cf0e5c08af6ec0d4768b.
2024-03-23 19:26:20 +00:00
Florian Hahn
39c8e87717
[VPlan] Move recording of Inst->VPValue to VPRecipeBuilder (NFCI). (#84464)
Instead of keeping a mapping of Inst->VPValues (of their corresponding
recipes) in VPlan's Value2VPValue mapping, keep it in VPRecipeBuilder
instead. After recently replacing the last user of this mapping after
initial construction, this mapping is only needed for recipe
construction (to map IR operands to VPValue operands).

By moving the mapping, VPlan's VPValue tracking can be simplified and
limited only to live-ins. It also allows removing disableValue2VPValue
and associated machinery & asserts.

PR: https://github.com/llvm/llvm-project/pull/84464
2024-03-23 18:43:14 +01:00