9 Commits

Author SHA1 Message Date
Andrei Safronov
0ba8b247dd
[Xtensa] Lowering FRAMEADDR/RETURNADDR operations. (#107363) 2024-09-13 21:33:54 +03:00
Andrei Safronov
ea625f48ab
[Xtensa] Implement sextload i8 (#106053) 2024-08-26 17:21:34 +02:00
Fangrui Song
c5a0c37b42 [Xtensa,test] Fix div.ll after #99981 2024-08-22 10:30:31 -07:00
Andrei Safronov
fab515ca7f
[Xtensa] Implement lowering Mul/Div/Shift operations. (#99981)
Implement lowering of the Mul/Div operations and also shift parts
operations. Implement lowering of the bit manipulations, like
ROT/SWAP/CTPOP/CTTZ/CTLZ.
2024-08-22 10:34:21 +02:00
Andrei Safronov
ce92b2f594
[Xtensa] Implement lowering SELECT_CC, SETCC. (#97017) 2024-07-11 09:46:24 +02:00
Andrei Safronov
cc8fdd60c2
[Xtensa] Lower GlobalAddress/BlockAddress/JumpTable (#95256)
This patch implements lowering of the GlobalAddress, BlockAddress,
JumpTable and BR_JT. Also patch adds legal support of the BR_CC
operation for i32 type.
2024-06-25 12:21:33 +02:00
Andrei Safronov
78f5d9cdba
[PATCH] [Xtensa] Implement FrameLowering methods and stack operation lowering. (#92960)
Implement emitPrologue/emitEpilogue methods, determine/spill/restore
callee saved registers functionality with test. Also implement lowering
of the DYNAMIC_STACKALLOC/STACKSAVE/STACKRESTORE stack operations with
tests.
2024-06-04 16:44:59 +02:00
Andrei Safronov
36209d366d
[Xtensa] Implement base CallConvention. (#83280)
Implement base Calling Convention functionality. 
Implement stack load/store register operations.
Implement call lowering.
2024-04-24 00:00:59 +02:00
Andrei Safronov
b5046a7fa9
[Xtensa] Initial codegen support from IR (#78548)
This PR provides implementation of the basic codegen infra such as
TargetFrameLowering, MCInstLower,
AsmPrinter, RegisterInfo, InstructionInfo, TargetLowering,
SelectionDAGISel.

Migrated from https://reviews.llvm.org/D145658
2024-02-12 17:41:59 +01:00