531682 Commits

Author SHA1 Message Date
tangaac
e3bd1f2b3f
[LoongArch] lower vector shuffle to zero or any extend (#129485) 2025-03-24 14:29:11 +08:00
Akshat Oke
174110bf3c
[CodeGen][NPM] Port LiveDebugValues to NPM (#131563) 2025-03-24 11:34:45 +05:30
Kazu Hirata
3c2731ce46
[AMDGPU] Avoid repeated hash lookups (NFC) (#132657) 2025-03-23 22:30:09 -07:00
Lang Hames
ef3e521a2b [ORC-RT] Add unique_function utility to the ORC runtime.
A bare-bones version of LLVM's unique_function: this behaves like a
std::unique_function, except that it supports move only callable types.

This will be used in upcoming improvements to the ORC runtime.
2025-03-24 15:46:43 +11:00
Kazu Hirata
1019457891
[CodeGen] Use *Set::insert_range (NFC) (#132651)
We can use *Set::insert_range to collapse:

  for (auto Elem : Range)
    Set.insert(E);

down to:

  Set.insert_range(Range);
2025-03-23 21:20:44 -07:00
Shoreshen
054e0b41a8
[AMDGPU] Add all type for bitcast on VReg_512 (#131775)
Add all types pattern for bitcast on VReg_512
2025-03-24 11:52:10 +08:00
Lang Hames
5d8e8e82e1 [ORC-RT] Rename extensible_rtti.{h,cpp} to rtti.{h,cpp}. NFCI.
The "extensible_" prefix on these files was inherited from LLVM, where it
distinguished the dynamic RTTI APIs from the LLVM's custom static RTTI APIs.

In the ORC runtime these files will be used to hold all of our RTTI APIs
(the current dynamic ones, and any static ones added in the future), so we
shouldn't use this prefix.
2025-03-24 13:49:23 +11:00
Lang Hames
36b1fb5c7a [ORC-RT] Fix typos in file comments. NFC. 2025-03-24 13:49:23 +11:00
A. Jiang
e409464e95
[libc++][test][NFC] Introduce TEST_STD_AT_LEAST_26_OR_RUNTIME_EVALUATED (#132593)
And use it for test cases that became constant-evaluation-suitable due
to P2562R1.

`TEST_STD_AT_LEAST_(20|23)_OR_RUNTIME_EVALUATED` are the precedents.
2025-03-24 10:43:19 +08:00
Kazu Hirata
73dc2afd2c
[Transforms] Use *Set::insert_range (NFC) (#132652)
We can use *Set::insert_range to collapse:

  for (auto Elem : Range)
    Set.insert(E);

down to:

  Set.insert_range(Range);

In some cases, we can further fold that into the set declaration.
2025-03-23 19:42:53 -07:00
tangaac
943a70717c
[LoongArch] Pre-commit test for vector sext, zext (#131742) 2025-03-24 10:35:18 +08:00
Kazu Hirata
0175dce138
[ADT] Add a range constructor to SmallSetVector (#132645)
DenseSet recently gained a range constructor:

  DenseSet<T> Dest(llvm::from_range, Src);

This patch adds the same signature to SmallSetVector for consistency.
2025-03-23 19:12:53 -07:00
Mingming Liu
3b20ac00f9
[NFC]Don't use else after a return (#132644)
A trivial code clean-up per
https://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return
2025-03-23 18:34:52 -07:00
Austin
7a056895c5
[mlir] Fix typo of tests (NFC) (#132396) 2025-03-24 09:29:00 +08:00
Alan
b32cf75699
[LLVM-C][OCaml] Make LLVMMetadataKind consistent between C and OCaml (#132268)
- Move LLVMDISubrangeTypeMetadataKind to end of LLVMMetadataKind enum.
Inserting a new enum constant in the middle of the enum breaks the ABI for
that enum. Commit e298fc2 introduced this issue, which was revealed because
the OCaml binding tests failed.
- Bring OCaml bindings up to date with LLVMMetadataKind enum.
2025-03-23 21:20:56 -04:00
Craig Topper
9d92d4b01c
[RISCV] Add alias names for tdata1 and tdata3 CSRs. (#132525)
The RISC-V Debug Specification defines multiple names for these CSRs.
https://github.com/riscv/riscv-debug-spec/releases/tag/1.0
2025-03-23 16:59:28 -07:00
Kazu Hirata
41b76119ec
[llvm] Use range constructors for *Set (NFC) (#132636) 2025-03-23 15:50:34 -07:00
Fangrui Song
49ce038a1a
RISCVAsmParser: Replace "modifier" with "specifier" in diagnostics
Use the preferred "specifier" term for relocation specifier.

"Relocation modifier" suggests adjustments happen during the linker's
relocation step rather than the assembler's expression evaluation.
The term "relocation specifier" is preferred by Arm for :lower16: and
IBM AIX, and I am trying to standardize in MC.

Pull Request: https://github.com/llvm/llvm-project/pull/132565
2025-03-23 15:12:27 -07:00
Florian Hahn
06fd10f1da
[VPlan] Don't create ExtractElement recipes for scalar plans. (#131604)
ExtractElements are no-ops for scalar VPlans. Don't introduce them in 
handleUncountableEarlyExit if the plan has only a scalar VF.

This fixes a crash trying to compute the cost of ExtractElement after 26ecf978951b79.

PR: https://github.com/llvm/llvm-project/pull/131604
2025-03-23 22:00:02 +00:00
Kazu Hirata
549fc0c1f9
[ADT] Use SetVector::insert_range (NFC) (#132633) 2025-03-23 14:59:33 -07:00
Justin Fargnoli
ff25115ca0
[NVPTX] cleanup & canonicalize mov (#129344)
Use a `multiclass` to define `mov` and canonicalize the `mov`
instruction to always use the `b<bit-size>` suffix.
2025-03-23 14:53:00 -07:00
Martin Storsjö
ff3e2ba9eb Revert "[VPlan] Add transformation to narrow interleave groups. (#106441)"
This reverts commit dfa665f19c52d98b8d833a8e9073427ba5641b19.

This commit caused miscompilations in ffmpeg, see
https://github.com/llvm/llvm-project/pull/106441 for details.
2025-03-23 23:27:39 +02:00
David CARLIER
b2b3cb5f76
[compiler-rt][rtsan] memffd_create for linux interception. (#132571) 2025-03-23 20:37:48 +00:00
Nikolas Klauser
fb44f00641
[libc++] Add [[gnu::nodebug]] on type traits (#128502) 2025-03-23 21:01:25 +01:00
Fangrui Song
4781a8ebd0 MCValue: add setSpecifier to simplify code
This primarily simplifies backend evaluateAsRelocatableImpl.
2025-03-23 12:36:46 -07:00
Fangrui Song
dfae1f968e MCValue: Simplify code with getSubSym 2025-03-23 12:22:44 -07:00
Kazu Hirata
46880fe12b
[ADT] Add range constructors to *Set (#132623)
DenseSet recently gained a range constructor:

  DenseSet<T> Dest(llvm::from_range, Src);

This patch adds the same signature to SetVector, SmallPtrSet,
SmallSet, and StringSet for consistency.
2025-03-23 12:13:42 -07:00
Fangrui Song
b73e144bdf MCValue: Simplify code with getSubSym
MCValue::SymB is a MCSymbolRefExpr *, which might become MCSymbol * in
the future. Simplify some code that uses MCValue::SymB.
2025-03-23 12:13:13 -07:00
Sam Elliott
8a133882bb
[RISCV] Xqciint SystemRegs, Final Assembly Insts (#130867)
This adds the Xqciint system registers from the Xqci-0.7 spec, as well
as two leftover instructions: `qc.c.mret` and `qc.c.mnret`

Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
2025-03-23 12:04:06 -07:00
Fangrui Song
83c3ec1b07 [MC] Move isMemtag test to AArch64
And introduce MCValue::getAddSym & MCValue::getSubSym to simplify code.

We do not utilize the MCSymbol argument of needsRelocateWithSymbol
as it will go away in the future.
2025-03-23 11:59:21 -07:00
Fangrui Song
c39d393038 ELFObjectWriter: Remove relocation specifier test from shouldRelocateWithSymbol
It's the decision of backend needsRelocateWithSymbol whether the
STT_SECTION adjustment should be suppressed.

test/MC/AArch64/data-directive-specifier.s demonstrates how to test this
property.
2025-03-23 11:50:58 -07:00
Fangrui Song
e3966814d5 [test] Improve R_AARCH64_PLT32 and R_AARCH64_GOTPCREL32 tests 2025-03-23 11:41:12 -07:00
Fangrui Song
39df4945e1 [Xtensa] Rename VariantKind to Specifier
Follow the X86, Mips, and RISCV renaming.

> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly.

In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.

The parseSpecifier name follows Sparc.
2025-03-23 11:26:56 -07:00
Kazu Hirata
a578a75ab5
[Target] Use DenseSet instead of DenseMap (NFC) (#132619)
This patch uses DenseSet instead of DenseMap.  Note that the set of
Registers that map to true without this patch is the same as the set
of Registers that are present in the set with this patch.  This patch
is inspired by:

  commit d7879e524fbbc4c2790dac62343444191f736f00
  Author: Craig Topper <craig.topper@sifive.com>
  Date:   Wed Mar 19 08:32:09 2025 -0700
2025-03-23 11:05:33 -07:00
Ivan Butygin
0be69e532c
[support] SlowDynamicAPInt: use fully qualified namespaces for func definitions (#132575)
Found while trying to amalgamate support lib. And I think current code
style require it anyway.
2025-03-23 20:47:07 +03:00
Jonathan Schleifer
a187060de9
Allow direct dispatch for the ObjFW runtime (#126382)
Allow direct dispatch for the ObjFW runtime
2025-03-23 10:45:18 -07:00
Florian Hahn
206b42c98e
[LV] Use VPBuilder to create ComputeReductionResult. (NFC)
Update code to use VPBuilder, to simplify follow-up changes.
2025-03-23 16:10:07 +00:00
Hui
2f1416bbcd
[libc++] implement std::flat_set (#125241)
Co-authored-by: Louis Dionne <ldionne.2@gmail.com>
2025-03-23 14:45:21 +00:00
Kazu Hirata
0b181de206
[ExecutionEngine] Avoid repeated hash lookups (NFC) (#132587) 2025-03-23 07:37:51 -07:00
Kazu Hirata
0a08d71f2e
[DebugInfo] Avoid repeated hash lookups (NFC) (#132586) 2025-03-23 07:37:08 -07:00
Kazu Hirata
6ecc1ff0a4
[CodeGen] Avoid repeated hash lookups (NFC) (#132585) 2025-03-23 07:36:39 -07:00
Kazu Hirata
ce2c4ea658
[Analysis] Avoid repeated hash lookups (NFC) (#132584)
FirstSpecialInsts caches the first special instruction for each basic
block.  This patch "inlines" fill into getFirstSpecialInstruction, the
sole caller, to eliminate repeated hash lookups.
2025-03-23 07:36:19 -07:00
Koakuma
da01a185f1
[SPARC][IAS] Set correct ELF flag values for VIS & VIS2-enabled objects
Reviewers: brad0, s-barannikov, rorth

Reviewed By: s-barannikov

Pull Request: https://github.com/llvm/llvm-project/pull/130966
2025-03-23 21:02:02 +07:00
Koakuma
3853116259
[SPARC][Driver] Set correct IAS mode defaults for Linux and Free/OpenBSD (#130108)
On those OSes, clang should set the assembler to enable VIS by default.
This is already the case when clang calls an external assembler, so make
sure clang+IAS use the same defaults.

This should fix [issue #125124](https://github.com/llvm/llvm-project/issues/125124).
2025-03-23 20:56:40 +07:00
Sandeep Dasgupta
81d7eef134
Sub-channel quantized type implementation (#120172)
This is an implementation for [RFC: Supporting Sub-Channel Quantization
in
MLIR](https://discourse.llvm.org/t/rfc-supporting-sub-channel-quantization-in-mlir/82694).

In order to make the review process easier, the PR has been divided into
the following commit labels:

1. **Add implementation for sub-channel type:** Includes the class
design for `UniformQuantizedSubChannelType`, printer/parser and bytecode
read/write support. The existing types (per-tensor and per-axis) are
unaltered.
2. **Add implementation for sub-channel type:** Lowering of
`quant.qcast` and `quant.dcast` operations to Linalg operations.
3. **Adding C/Python Apis:** We first define he C-APIs and build the
Python-APIs on top of those.
4. **Add pass to normalize generic ....:** This pass normalizes
sub-channel quantized types to per-tensor per-axis types, if possible.


A  design note:
- **Explicitly storing the `quantized_dimensions`, even when they can be
derived for ranked tensor.**
While it's possible to infer quantized dimensions from the static shape
of the scales (or zero-points) tensor for ranked
data tensors
([ref](https://discourse.llvm.org/t/rfc-supporting-sub-channel-quantization-in-mlir/82694/3)
for background), there are cases where this can lead to ambiguity and
issues with round-tripping.

```
Consider the example: tensor<2x4x!quant.uniform<i8:f32:{0:2, 0:2}, {{s00:z00, s01:z01}}>>
```

The shape of the scales tensor is [1, 2], which might suggest that only
axis 1 is quantized. While this inference is technically correct, as the
block size for axis 0 is a degenerate case (equal to the dimension
size), it can cause problems with round-tripping. Therefore, even for
ranked tensors, we are explicitly storing the quantized dimensions.
Suggestions welcome!


PS: I understand that the upcoming holidays may impact your schedule, so
please take your time with the review. There's no rush.
2025-03-23 07:37:55 -05:00
Jonathan Cohen
7bda9caa49
Revert "[AArch64][MachineCombiner] Recombine long chains of accumulation instructions into a tree to increase ILP (#126060) (#132607)
This reverts commit c4caf949aa934a219e84d4ba0530bd535e698cdb.
2025-03-23 13:58:00 +02:00
Jonathan Cohen
c4caf949aa
[AArch64][MachineCombiner] Recombine long chains of accumulation instructions into a tree to increase ILP (#126060)
This pattern shows up often in media libraries. The optimization should only
kick in for O3. Currently only supports a single family of accumulation
instructions, but can easily be expanded to support additional
instructions in the future.
2025-03-23 13:25:35 +02:00
Florian Hahn
cfd53ffb44
[InstCombine] Use MapVector for SourceAggregates. (#132564)
foldAggregateConstructionIntoAggregateReuse iterates over the entries of
SourceAggregates and the order of inserted instructions depends on the
order of the iterator. Using a regular DenseMap can lead to
non-deterministic value naming/numbering.

I don't think it can actually impact the generated binary, but it makes
diffing IR more difficult.

PR: https://github.com/llvm/llvm-project/pull/132564
2025-03-23 11:16:50 +00:00
Letu Ren
bcd08f4d2c
[mlir][llvmir] Add SameOperandsAndResultType trait to LLVM_CountZerosIntrOp (#131133)
According to https://llvm.org/docs/LangRef.html#llvm-ctlz-intrinsic and
https://llvm.org/docs/LangRef.html#llvm-cttz-intrinsic, The return type
of `llvm.intr.ctlz` and `llvm.intr.cttz` must match the first argument
type.
2025-03-23 12:15:11 +01:00
Florian Hahn
c482b8faea
[VPlan] Only execute VPExpandSCEVRecipes once and remove them (NFC).
Instead of executing the whole entry VPIRBB twice, first only execute
the VPExpandSCEVRecipes and replace their uses with the expanded
VPValue, which will be a live-in. This allows removing special logic in
VPExpandSCEVRecipe to support executing twice and allows moving the
ExpandedSCEVs map out of VPTransformState.

It will also allow adding other recipes to the entry VPBB in the future.
2025-03-23 09:06:01 +00:00