1 Commits

Author SHA1 Message Date
Matt Arsenault
ff53086924
AMDGPU: Add new VA inline asm constraint for AV registers (#152665)
Add a new constraint corresponding to the AV_* register classes
for operands which can allocate AGPRs or VGPRs. This applies
to load and stores on gfx90a+, and srcA / srcB for MFMA instructions.

The error emitted on unsupported targets isn't ideal, it is
produced by the register allocator without a rationale, but it is
consistent with the existing errors.

I mostly want this for writing allocation tests.
2025-08-12 10:17:28 +09:00