This adds CIR handling for the __builtin_flt_rounds and
__builtin_set_flt_rounds builtin functions. Because the LLVM dialect
does not have dedicated operations for these, I have chosen not to
implement them as operations in CIR either. Instead, we just call the
LLVM intrinsic.
This PR adds CIRGenBuiltinRISCV.cpp file for RISCV specific builtins
codegen support.
List all builtins except vector builtins which need tablegen, and mark
them as "NYI".
Replace the monolithic cir.binop.overflow operation and its
BinOpOverflowKind enum with three individual operations:
cir.add.overflow, cir.sub.overflow, and cir.mul.overflow.
This follows the same pattern used when BinOp and UnaryOp were
previously split into per-operation ops (cir.add, cir.sub, etc.),
eliminating enum dispatch and enabling per-op traits like Commutative.
Split the monolithic cir.unary operation (which dispatched on a
UnaryOpKind enum) into four separate operations: cir.inc, cir.dec,
cir.minus, and cir.not.
Changes:
- Add CIR_UnaryOpInterface with getInput()/getResult() methods
- Add CIR_UnaryOp and CIR_UnaryOpWithOverflowFlag base classes
- Define IncOp, DecOp, MinusOp, NotOp with per-op folds
- Add Involution trait to NotOp for not(not(x)) -> x folding
- Replace createUnaryOp() with createInc/Dec/Minus/Not builders
- Split LLVM lowering into four separate patterns
- Split LoweringPrepare complex-type handling per unary op
- Update CIRCanonicalize and CIRSimplify for new op types
- Update all codegen files to use bool params instead of UnaryOpKind
- Remove CIR_UnaryOpKind enum and old CIR_UnaryOp definition
Assembly format change:
cir.unary(inc, %x) nsw : !s32i, !s32i -> cir.inc nsw %x : !s32i
cir.unary(not, %x) : !u32i, !u32i -> cir.not %x : !u32i
This showed up on a benchmark, so getting it out of the way. bzero just
does a memset-0, so this lowers to the cir.libc.memset intrinsic. Tests
added were from the classic codegen with improved check lines.
We were attempting to capture a `count` argument for __builtin_va_start
but the builtin doesn't actually have that as a defined argument. This
change removes the errant handling.
Replace the single `cir.binop` operation (dispatched via a `BinOpKind`
enum) with nine distinct ops — `cir.add`, `cir.sub`, `cir.mul`,
`cir.div`, `cir.rem`, `cir.and`, `cir.or`, `cir.xor`, and `cir.max` —
each with precise type constraints and only the attributes it needs
(nsw/nuw/sat on add/sub via `BinaryOverflowOp`).
A new `BinaryOpInterface` provides uniform `getLhs`/`getRhs`/`getResult`
access for passes and analyses.
The monolithic switch-based CIRToLLVMBinOpLowering is replaced by per-op
patterns generated through the existing CIRLowering.inc TableGen
infrastructure, with shared dispatch factored into two helpers:
`lowerSaturatableArithOp` for add/sub and `lowerIntFPBinaryOp` for
div/rem.
This adds `__builtin_reduce_[in_order|assoc]_fadd` to expose the
`llvm.vector.reduce.fadd.*` intrinsic directly in Clang, for the full
range of supported FP types.
Given a floating-point vector `vec` and a scalar floating-point value
`acc`:
- `__builtin_reduce_assoc_fadd(vec)` corresponds to an fast/associative
reduction
* i.e, the fadds can occur in any order
- `__builtin_reduce_in_order_fadd(vec, acc)` corresponds to an ordered
redunction
* i.e, the result is as-if an accumulator was initialized with `acc`
and each lane was added to it in-order, starting from lane 0
As support for RAII FP options has been upstreamed (#179121), this patch
removes `CIRGenFPOptionsRAII` from the `MissingFeatures` list and
updates its expected constructor sites.
## Summary
This PR adds support for non-floating-point builtin intrinsics as a
follow-up to #175233:
- Integer `abs`/`labs`/`llabs` with `cir.abs` operation
- `__builtin_unpredictable` handling
- Integer elementwise abs support
- Tests: `builtin-rotate.c`, `pred-info-builtins.c`, updates to `libc.c`
and `builtins-elementwise.c`
## Dependency
**This PR depends on #175233 (FP math builtins) and should be merged
after it.**
The non-FP builtins were split from #175233 per reviewer feedback to
reduce PR size.
## Test plan
- [x] All CIR codegen tests pass
- [x] All CIR tests pass
Previously we were generating a signed 1-bit integer constant for
builtin expressions that returned a boolean value. This caused a
verification error of mismatched types when we tried to store this
constant result to a pointer-to-bool location. This change adds a check
for boolean types.
This patch adds synchronization scope support to the `cir.atomic.fetch`
operation.
Most of the new test code in `atomic-scoped.c` is generated by an AI
agent. The generated tests are manually reviewed and verified.
Assisted-by: Copilot with GPT-5.2-Codex
This PR upstreams the generic intrinsic emission path and tests it for
the rdpmc builtin. The incubator has llvm_unreachable("NYI") when the
intrinsic return type doesn't match. This PR adds the type coercion to
handle that case.
tryEvaluateString was returning an std::optional, but the other try* API
was not. Update tryEvaluateObjectSize and tryEvaluateStrLen to return an
std::optional<uint64_t>.
Upstreaming ClangIR PR : https://github.com/llvm/clangir/pull/2030
This PR adds CIRGenBuiltinAMDGPU.cpp file for AMDGPU specific builtin
codegen support.
Lists out all the builtins that are currently supported for codegen in
`clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp`.
All builtins codegen are currently "NYI".
Adds CIR `ClearCacheOp` and lowers `__builtin___clear_cache` through CIR
to the LLVM `llvm.clear_cache` intrinsic. Includes codegen + lowering
support and a test.
This PR adds support for the memchr builtin functions:
## Changes
- Define `CIR_MemChrOp` (`cir.libc.memchr`) operation in CIROps.td
- Add builtin handling for `__builtin_char_memchr` and
`__builtin_memchr` in CIRGenBuiltin.cpp
- Add LLVM lowering to call the `memchr` library function
- Add CodeGen and IR tests with CIR, LLVM, and OGCG checks
The operation searches for a pattern byte in a memory region and returns
a pointer to the first occurrence or null.
Adds support for several `__sync_<OP>_and_fetch` builtins, and several helper methods for emitting atomic fetch + arithmetic operations.
---------
Co-authored-by: Andy Kaylor <akaylor@nvidia.com>
- Support CIR codegen for follow atomic fence builtin when the memory
order is non constant: `__atomic_thread_fence` `__atomic_signal_fence`
`__c11_atomic_thread_fence` `__c11_atomic_signal_fence`
- Refactor current implementation when the memory order is constant, the
argument expression at AST is evaluated as a constant directly.
- Merge both static memory order implementation and dynamic's into one
interface `emitAtomicExprWithMemOrder`
- Add test cases that cover all kinds of memory order.
Depending on the compiler CLI options, attributes near the call site and
pragmas we might not be allowed to emit a call to an intrinsic (e.g. if
it does not set errno and we expect it to be set). This is checked by
`shouldGenerateFPMathIntrinsic` (shared with classing codegen).
This commit adds this check and additionally adds remaining cases in the
switch statement for math builtins.
- Add new `CIR_AddrOfReturnAddrOp` and support lowering it to LLVMIR
- Add CIR CodeGen for `_AddressOfReturnAddress` X86 builtin
- Fix error return type of `FrameAddrOp`, and add missing test for
`_ReturnAddress`
Part of https://github.com/llvm/llvm-project/issues/167765
- Support CIR codegen for follow X86 builtin: `_ReadWriteBarrier`
`_ReadBarrier` `_WriteBarrier` `__faststorefence`
- CIR dialect operations may have no results, no values will be returned
after `emitTargetBuiltinExpr` even if it executes successfully. Using
`std::optional<mlir::Value>` as return type to reslove this problem.
- Part of [#167765](https://github.com/llvm/llvm-project/issues/167765)
This change adds the basic code structure for handling AArch64 builtins.
The structure of this code is brought over from classic codegen to make
implementing missing builtins easier. In some cases, the handling
involved too much logic for a simple NFC change, so those parts were
replaced with a MissingFeature assert.
The actual handling for all builtins is left for later changes.
This PR adds codegen for `cir.await` ready and suspend. One notable
difference from the classic codegen is that, in the suspend branch, it
emits an `AwaitSuspendWrapper`(`.__await_suspend_wrapper__init`)
function that is always inlined. This function wraps the suspend logic
inside an internal wrapper that gets inlined. Example here:
https://godbolt.org/z/rWYGcaaG4
This PR adds a number of cases to the switch statement in
`CIRGenBUiltin.cpp`. Some existing cases were relocated, so the order
matches the order from the switch statement in clangs codegen.
Additionally, some exisiting cases were moved to functions, to keep the
code a little cleaner. In the future, it will be easier to keep track of
which builtins have not been implemented, since there would always be a
NYI case for unimplemented builtins.
Ref commit in incubator: ee17ff67f3e567585db991cdad1159520c516bb4
There is a minor change in the assumption for emitting a direct callee.
In incubator, `bool hasAttributeNoBuiltin = false`
(`llvm-project/clang/lib/CIR/CodeGen/CIRGenExpr.cpp:1671`), while in
upstream, it's true, therefore, the call to finite(...) is not converted
to a builtin anymore.
Fixes#163892
related: #160386
Add support for address space conversions in CIR.
- Added `createAddrSpaceCast` methods to `CIRBaseBuilderTy` to handle
address space conversions
- Implemented address space conversion handling in `emitCastLValue` and
`VisitCastExpr`
- Added `performAddrSpaceCast` method to `TargetCIRGenInfo` for
target-specific address space casting
- Added `getLangTempAllocaAddressSpace` to `CIRGenModule` to get the
language-specific address space for temporary allocations
- Added a test file `address-space-conversion.cpp` to verify address
space conversion functionality
* Add cir.objsize operation to CIR dialect
* Add lowering for cir.objsize operation to LLVM dialect
* Add codegen for __builtin_object_size and
__builtin_dynamic_object_size
Note that this does not support the pass_object_size attribute yet.
---------
Co-authored-by: Andy Kaylor <akaylor@nvidia.com>
