464979 Commits

Author SHA1 Message Date
Mark de Wever
ffe0495105 [NFC][libc++] Addresses LWG3927.
Changes to preconditions have no impact on the library.

Implements
- LWG3927 Unclear preconditions for operator[] for sequence containers

Reviewed By: #libc, philnik

Differential Revision: https://reviews.llvm.org/D153286
2023-06-20 17:19:55 +02:00
Mark de Wever
946116fc05 [NFC][libc++] Addresses LWG3935.
Note libc++ implemented this in its initial version.

Implements
- LWG3935 template<class X> constexpr complex& operator=(const complex<X>&) has no specification

Reviewed By: #libc, philnik, ldionne

Differential Revision: https://reviews.llvm.org/D153287
2023-06-20 17:16:06 +02:00
Nikita Popov
3fbbfa7f24 [SafepointIRVerifier] Convert test to opaque pointers (NFC) 2023-06-20 17:15:21 +02:00
Simon Pilgrim
43ad2e9c8b [DAG] Add getExtOrTrunc helper. NFC.
Wrap the getSExtOrTrunc/getZExtOrTrunc calls behind an IsSigned argument.
2023-06-20 16:03:18 +01:00
Nikita Popov
135aaff2b5 [LTO] Avoid -opaque-pointers=0 in test (NFC)
Commit the bitcode file instead of generating it dynamically, as
this will no longer be possible in the future.
2023-06-20 17:03:04 +02:00
Louis Dionne
2da049a141 [libc++] Add incomplete availability markup for std::pmr
This fixes rdar://110330781, which asked for the feature-test macro
for std::pmr to take into account the deployment target. It doesn't
fix https://llvm.org/PR62212, though, because the availability markup
itself must be disabled until some Clang bugs have been fixed.

This is pretty vexing, however at least everything should work once
those Clang bugs have been fixed. In the meantime, this patch at least
adds the required markup (as disabled) and ensures that the feature-test
macro for std::pmr is aware of the deployment target requirement.

Differential Revision: https://reviews.llvm.org/D135813
2023-06-20 10:59:05 -04:00
Nikita Popov
db3bbdcd4f [DebugInfo] Convert tests to opaque pointers (NFC) 2023-06-20 16:51:05 +02:00
Nikita Popov
aa79ad4d1a [Bitcode] Remove -opaque-pointer=0 check lines (NFC)
These tests were testing both typed an opaque pointers. Only keep
opaque pointers tests.
2023-06-20 16:43:14 +02:00
Nikita Popov
b9648c70d1 [llvm-nm] Avoid -opaque-pointers option in test (NFC)
Commit the typed pointer bitcode file instead of producing it,
as this will not be possible in the future anymore.
2023-06-20 16:35:54 +02:00
Simon Pilgrim
ff23856c1c [DAG] Fold (abds x, y) -> (abdu x, y) iff both args are known positive
This is a generic DAG combine version of D151055 which recognizes when a signed ABDS can be safely replaced with a unsigned ABDU instruction if it is legal.

Alive2: https://alive2.llvm.org/ce/z/pb5BjG

Differential Revision: https://reviews.llvm.org/D153328
2023-06-20 15:31:22 +01:00
David Green
3095dd026c [AArch64] Use ISD::isExtOpcode. NFC 2023-06-20 15:26:01 +01:00
Jingu Kang
cce08185b4 [AArch64] Try to fold uaddlv and uaddlp
Add tablegen pattern for uaddlv(uaddlp(x)) ==> uaddlv(x).

Differential Revision: https://reviews.llvm.org/D153323
2023-06-20 15:14:27 +01:00
Stephen Thomas
fed6cd9c15 [AMDGPU] Remove unused method Waitcnt::dominates(). NFC
Differential Revision: https://reviews.llvm.org/D153322
2023-06-20 15:10:56 +01:00
Weining Lu
3dd319ecf3 [LoongArch] Optimize conditional selection of integer
This patch optimizes code generation by leveraging the zeroing behavior of the `maskeqz`/`masknez` instructions.

```
int sel(int a, int b)
{
    return (a < b) ? a : 0;
}
```

```
slt	$a1,$a0,$a1
masknez	$a2,$r0,$a1
maskeqz	$a0,$a0,$a1
or	$a0,$a0,$a2
```

=>

```
slt	$a1,$a0,$a1
maskeqz	$a0,$a0,$a1
```

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D153193
2023-06-20 21:54:40 +08:00
Pravin Jagtap
699addeff0 [AMDGPU] Use verify<domtree> instead of intra-pass asserts.
Verifying dominator tree is expensive using intra-pass
asserts. Asserts added during D147408 are
increasing the build time of libc significantly. This change
does the verification after the atomic optimizer pass
and should fix the regression reported in D153232.

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D153261
2023-06-20 09:52:58 -04:00
Weining Lu
1f1385d932 [LoongArch] Indent LoongArchInstrInfo.td a little bit. NFC 2023-06-20 21:49:43 +08:00
Tue Ly
46aa659a32 [libc][math] Improve exp2f performance.
Re-organize special cases and add a special case when `|x| < 2^-5`.

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D153134
2023-06-20 09:34:20 -04:00
Tue Ly
0ae409c0d7 [libc][math] Slightly improve sinhf and coshf performance.
Re-order exceptional branches and slightly adjust the evaluation.
Depends on https://reviews.llvm.org/D153026 .

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D153062
2023-06-20 09:27:28 -04:00
Tue Ly
5dbd5118ec [libc][math] Improve tanhf performance.
Re-order exceptional branches and slightly adjust the evaluation.

Performance tested with the CORE-MATH project on AMD EPYC 7B12 (clocks/op)

Reciprocal throughputs:
```
--- BEFORE ---

$ CORE_MATH_PERF_MODE=rdtsc ./perf.sh tanhf
[####################] 100 %  (with -mavx2 -mfma)
Ntrial = 20 ; Min = 7.794 + 0.102 clc/call; Median-Min = 0.066 clc/call; Max = 8.267 clc/call;
[####################] 100 %. (with -msse4.2)
Ntrial = 20 ; Min = 10.783 + 0.172 clc/call; Median-Min = 0.144 clc/call; Max = 11.446 clc/call;
[####################] 100 %. (SSE2)
Ntrial = 20 ; Min = 18.926 + 0.381 clc/call; Median-Min = 0.342 clc/call; Max = 19.623 clc/call;

--- AFTER ---

$ CORE_MATH_PERF_MODE=rdtsc ./perf.sh tanhf
[####################] 100 %  (with -mavx2 -mfma)
Ntrial = 20 ; Min = 6.598 + 0.085 clc/call; Median-Min = 0.052 clc/call; Max = 6.868 clc/call;
[####################] 100 %  (with -msse4.2)
Ntrial = 20 ; Min = 9.245 + 0.304 clc/call; Median-Min = 0.248 clc/call; Max = 10.675 clc/call;
[####################] 100 %. (SSE2)
Ntrial = 20 ; Min = 11.724 + 0.440 clc/call; Median-Min = 0.444 clc/call; Max = 12.262 clc/call;
```

Latency:
```
--- BEFORE ---

$ PERF_ARGS="--latency" CORE_MATH_PERF_MODE=rdtsc ./perf.sh tanhf
[####################] 100 %  (with -mavx2 -mfma)
Ntrial = 20 ; Min = 38.821 + 0.157 clc/call; Median-Min = 0.122 clc/call; Max = 39.539 clc/call;
[####################] 100 %. (with -msse4.2)
Ntrial = 20 ; Min = 44.767 + 0.766 clc/call; Median-Min = 0.681 clc/call; Max = 45.951 clc/call;
[####################] 100 %. (SSE2)
Ntrial = 20 ; Min = 55.055 + 1.512 clc/call; Median-Min = 1.571 clc/call; Max = 57.039 clc/call;

--- AFTER ---

$ PERF_ARGS="--latency" CORE_MATH_PERF_MODE=rdtsc ./perf.sh tanhf
[####################] 100 %  (with -mavx2 -mfma)
Ntrial = 20 ; Min = 36.147 + 0.194 clc/call; Median-Min = 0.181 clc/call; Max = 36.536 clc/call;
[####################] 100 %  (with -msse4.2)
Ntrial = 20 ; Min = 40.904 + 0.728 clc/call; Median-Min = 0.557 clc/call; Max = 42.231 clc/call;
[####################] 100 %. (SSE2)
Ntrial = 20 ; Min = 55.776 + 0.557 clc/call; Median-Min = 0.542 clc/call; Max = 56.551 clc/call;
```

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D153026
2023-06-20 09:25:07 -04:00
Weining Lu
2efdacf74c [LoongArch] Add missing chains and remove unnecessary SDNPSideEffect property for some intrinsic nodes 2023-06-20 21:16:26 +08:00
David Green
1d27ad2077 [AArch64] Add tablegen patterns for fp16 fcvtn2.
Similar to the existing f32 pattern, this adds a tablegen pattern for the fp16
fcvtn2.
2023-06-20 14:10:25 +01:00
Simi Pallipurath
8cf8956897 [lld][Arm] Big Endian - Byte invariant support.
Arm has BE8 big endian configuration called a byte-invariant(every byte has the same address on little and big-endian systems).

When in BE8 mode:
  1. Instructions are big-endian in relocatable objects but
     little-endian in executables and shared objects.
  2. Data is big-endian.
  3. The data encoding of the ELF file is ELFDATA2MSB.

To support BE8 without an ABI break for relocatable objects,the linker takes on the responsibility of changing the endianness of instructions. At a high level the only difference between BE32 and BE8 in the linker is that for BE8:
  1. The linker sets the flag EF_ARM_BE8 in the ELF header.
  2. The linker endian reverses the instructions, but not data.

This patch adds BE8 big endian support for Arm. To endian reverse the instructions we'll need access to the mapping symbols. Code sections can contain a mix of Arm, Thumb and literal data. We need to endian reverse Arm instructions as words, Thumb instructions
as half-words and ignore literal data.The only way to find these transitions precisely is by using mapping symbols. The instruction reversal will need to take place after relocation. For Arm BE8 code sections (Section has SHF_EXECINSTR flag ) we inserted a step after relocation to endian reverse the instructions. The implementation strategy i have used here is to write all sections BE32  including SyntheticSections then endian reverse all code in InputSections via mapping symbols.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D150870
2023-06-20 14:08:21 +01:00
Joseph Huber
efacdfc235 [LinkerWrapper] Support linking vendor bitcode late
The GPU vendors currently provide bitcode files for their device
runtime. These files need to be handled specially as they are not built
to be linked in with a standard `llvm-link` call or through LTO linking.
This patch adds an alternative to use the existing clang handling of
these libraries that does the necessary magic to make this work.

We do this by causing the LTO backend to emit bitcode before running the
backend. We then pass this through to clang which uses the existing
support which has been fixed to support this by D152391. The backend
will then be run with the merged module.

This patch adds the `--builtin-bitcode=<triple>=file.bc` to specify a single
file, or just `--clang-backend` to let the toolchain handle its defaults
(currently nothing for NVPTX and the ROCm device libs for AMDGPU). This may have
a performance impact due to running the optimizations again, we could
potentially disable optimizations in LTO and only do the linking if this is an
issue.

This should allow us to resolve issues when relying on the `linker-wrapper` to
do a late linking that may depend on vendor libraries.

Depends on D152391

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D152442
2023-06-20 08:02:59 -05:00
Joseph Huber
8784b6a854 [Clang] Allow bitcode linking when the input is LLVM-IR
Clang provides the `-mlink-bitcode-file` and `-mlink-builtin-bitcode`
options to insert LLVM-IR into the current TU. These are usefuly
primarily for including LLVM-IR files that require special handling to
be correct and cannot be linked normally, such as GPU vendor libraries
like `libdevice.10.bc`. Currently these options can only be used if the
source input goes through the AST consumer path. This patch makes the
changes necessary to also support this when the input is LLVM-IR. This
will allow the following operation:

```
clang in.bc -Xclang -mlink-builtin-bitcode -Xclang libdevice.10.bc
```

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D152391
2023-06-20 08:02:58 -05:00
Matthias Springer
87da4b6fa6 [mlir][Pass] Check supported op types before running a pass
Add extra error checking to prevent passes from being run on unsupported ops through the pass manager infrastructure.

Differential Revision: https://reviews.llvm.org/D153144
2023-06-20 14:40:11 +02:00
Haojian Wu
149f309f50 [include-cleaner] Ignore the ParmVarDecl itself in WalkAST.cpp
This fixes a false positive where a ParamVarDecl happend to be the
same name of some C standard symbol and has a global namespace.

```
using A = int(int time); // we suggest <ctime> for the `int time`.
```

Differential Revision: https://reviews.llvm.org/D153330
2023-06-20 14:26:55 +02:00
Vladislav Dzhidzhoev
6bea8331f9 Revert "Reland "[DebugMetadata][DwarfDebug] Support function-local types in lexical block scopes (4/7)" (2)"
This reverts commit cb9ac7051589ea0d05507f9370d0716bef86b4ae.
It causes an assert in clang:
virtual void llvm::DwarfDebug::endFunctionImpl(const llvm::MachineFunction*): Assertion `LScopes.getAbstractScopesList().size() == NumAbstractSubprograms && "getOrCreateAbstractScope() inserted an abstract subprogram scope"' failed.
https://bugs.chromium.org/p/chromium/issues/detail?id=1456288#c2
2023-06-20 13:08:47 +02:00
Alexey Lapshin
f6c1796b44 [DWARFLinker] add DWARFUnit::getIndexedAddressOffset().
This patch is a followup for D153162. It cures one more place
where indexed address was incorrectly read. It also moves handling
of indexed address into DWARFUnit.

Differential Revision: https://reviews.llvm.org/D153297
2023-06-20 13:03:12 +02:00
Alex Zinenko
e2b19ef6ac [mlir] mark libraries in mlir/examples as such
LLVM build system separates between `add_llvm_example_library` and
`add_llvm_library`, which is presumably used to package examples
separately from the regular library. Introduce a similar approach to
building example libraries in MLIR and use it for the transform dialect
tutorial.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D153265
2023-06-20 13:02:42 +02:00
Harvin Iriawan
ef9159c7f6 [AArch64] Add Cortex-A510 specific scheduling
- Update the Cortex-A510 mcpu target to use A510 scheduling info instead of
  A55. Values taken are based on the A510 software optimisation guide
  https://developer.arm.com/documentation/PJDOC-466751330-536816/latest
- Make latency of most integer ops to 1. CPU uarch is able to resolve most
  integer ops in 1 cycle

Differential Revision: https://reviews.llvm.org/D152688
2023-06-20 11:48:18 +01:00
ManuelJBrito
36d50348a8 [clang][NFC] Drop alignment in builtin-nondeterministic-value test
Drop alignment to allow test to run in different platforms.

Differential Revision: https://reviews.llvm.org/D152547
2023-06-20 11:38:37 +01:00
Chuanqi Xu
b6f30623af [Coroutines] Store the index for final suspend point in the exception path
Try to address part of
https://github.com/llvm/llvm-project/issues/61900.

It is not completely addressed since the original reproducer is not
fixed due to the final suspend point is optimized out in its special
case. But that is a relatively independent issue.
2023-06-20 18:38:05 +08:00
Ivan Kosarev
2d3e6c4402 [AMDGPU] Drop GFX11 runs for dagcombine-fma-fmad.ll and fma.f16.ll.
They cause failures on the llvm-clang-x86_64-expensive-checks-debian
buildbot.

This partially reverts
D153269 [AMDGPU][GFX11] Add test coverage for FMA instructions.
2023-06-20 11:32:44 +01:00
Jan Svoboda
1c64c414ed [clang][index] Fix cast warning
This is a follow-up to D151938 that should fix GCC's -Wcast-qual warning.
2023-06-20 12:22:18 +02:00
Francesco Petrogalli
c7430ff9bf [CodeGen][test] Add missing REQUIRES.
Differential Revision: https://reviews.llvm.org/D153325
2023-06-20 12:00:07 +02:00
Ivan Kosarev
dec42ffa28 [AMDGPU][GFX11] Add test coverage for FMA instructions.
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D153269
2023-06-20 10:50:03 +01:00
Francesco Petrogalli
37db9cae2b [llc][MISched] Add -misched-detail-resource-booking to llc.
The option `-misched-detail-resource-booking` prints the following
information every time the method
`SchedBoundary::getNextResourceCycle` is invoked:

1. counters of the resources that have already been booked;

2. the values returned by `getNextResourceCycle`, which is the next
available cycle in which a resource can be booked.

The method is useful to debug low-level checks inside the machine
scheduler that make decisions based on the values returned by
`getNextResourceCycle`.

Reviewed By: andreadb

Differential Revision: https://reviews.llvm.org/D153116
2023-06-20 11:46:27 +02:00
Francesco Petrogalli
25f8b1a0a8 Revert "[llc][MISched] Add -misched-detail-resource-booking to llc."
Reverting because of https://lab.llvm.org/buildbot#builders/75/builds/32485:

llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:2374:7: error: use of undeclared identifier 'MischedDetailResourceBooking'
 if (MischedDetailResourceBooking)

This reverts commit fc06262c1c365777e71207b6a5de281cba927c96.
2023-06-20 11:28:45 +02:00
Francesco Petrogalli
fc06262c1c [llc][MISched] Add -misched-detail-resource-booking to llc.
The option `-misched-detail-resource-booking` prints the following
information every time the method
`SchedBoundary::getNextResourceCycle` is invoked:

1. counters of the resources that have already been booked;

2. the values returned by `getNextResourceCycle`, which is the next
available cycle in which a resource can be booked.

The method is useful to debug low-level checks inside the machine
scheduler that make decisions based on the values returned by
`getNextResourceCycle`.

Reviewed By: andreadb

Differential Revision: https://reviews.llvm.org/D153116
2023-06-20 11:13:39 +02:00
Matthias Springer
c63d2b2c71 [mlir][transform] Add TransformRewriter
All `apply` functions now have a `TransformRewriter &` parameter. This rewriter should be used to modify the IR. It has a `TrackingListener` attached and updates the internal handle-payload mappings based on rewrites.

Implementations no longer need to create their own `TrackingListener` and `IRRewriter`. Error checking is integrated into `applyTransform`. Tracking listener errors are reported only for ops with the `ReportTrackingListenerFailuresOpTrait` trait attached, allowing for a gradual migration. Furthermore, errors can be silenced with an op attribute.

Additional API will be added to `TransformRewriter` in subsequent revisions. This revision just adds an "empty" `TransformRewriter` class and updates all `apply` implementations.

Differential Revision: https://reviews.llvm.org/D152427
2023-06-20 10:49:59 +02:00
Nikita Popov
06ebed3e55 [SCEVNormalization] Short circuit case with no loops (NFC)
If there are no post-inc loops, normalization is a no-op. Don't
bother rewriting the SCEV in that case.
2023-06-20 10:48:16 +02:00
Diana Picus
041bfe40a7 [AMDGPU] Document amdgpu_cs_chain[_preserve] CCs. NFC
Co-authored-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Differential Revision: https://reviews.llvm.org/D151997
2023-06-20 10:45:58 +02:00
Diana Picus
5c5eff44ce [AMDGPU] Start documenting calling conventions. NFC
Add a section to AMDGPUUsage.rst about calling conventions and list the
ones from the CallingConv enum. Full descriptions can come later (help
appreciated).

Differential Revision: https://reviews.llvm.org/D151996
2023-06-20 10:45:58 +02:00
serge-sans-paille
f6be0814c3
[llvm-profdata] Fix llvm-profdata help and make sure it remains in sync
This makes the new `order` subcommand part of the help.
As a side effect, also make llvm::map_range compatible with plain
arrays.

Differential Revision: https://reviews.llvm.org/D153303
2023-06-20 10:25:29 +02:00
Michael Buch
c146df9618 [clang][DebugInfo] Emit DW_AT_deleted on any deleted member function
Currently we emit `DW_AT_deleted` for `deleted` special-member
functions (i.e., ctors/dtors). However, in C++ one can mark any
member function as deleted. This patch expands the set of member
functions for which we emit `DW_AT_deleted`.

The DWARFv5 spec section 5.7.8 says:
```
<non-normative>
In C++, a member function may be declared as deleted. This prevents the compiler from
generating a default implementation of a special member function such as a constructor
or destructor, and can affect overload resolution when used on other member functions.
</non-normative>

If the member function entry has been declared as deleted, then that entry has a
DW_AT_deleted attribute.
```

Thus this change is conforming.

Differential Revision: https://reviews.llvm.org/D153282
2023-06-20 09:19:19 +01:00
Nuno Lopes
189d9447b1
[docs] Fix GEP faq references to undefined behavior [NFC] 2023-06-20 09:07:08 +01:00
Ben Shi
6d05f3f56e [CSKY] Optimize multiplication with immediates
Try to break a multiplication with a specific immediate to
an/a addition/subtraction of left shifts.

Reviewed By: zixuan-wu

Differential Revision: https://reviews.llvm.org/D153106
2023-06-20 16:03:31 +08:00
Ben Shi
56e33d9881 [CSKY][test][NFC] Add more tests of multiplication with immediates
Reviewed By: zixuan-wu

Differential Revision: https://reviews.llvm.org/D153105
2023-06-20 16:03:15 +08:00
Diana Picus
99610fa77d Revert "[AMDGPU] Start documenting calling conventions. NFC"
This reverts commit aa7b127cb7314e326457d7f790d36db1cb74f63c.

...because I really ought to install sphinx.
2023-06-20 09:55:52 +02:00
Martin Braenne
aad5141745 Revert "Prevent deadlocks in death tests."
This reverts commit dfbcee286b9b96751014ebc5ba5290e42796be37.

This was causing unit tests to fail on Gentoo, see comments on
https://reviews.llvm.org/D152696.
2023-06-20 07:39:31 +00:00