db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
23 lines
862 B
LLVM
23 lines
862 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-android | FileCheck %s
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declare <2 x i16> @llvm.fshl.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
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define <2 x i16> @rotlv2_16(<2 x i16> %vec2_16, <2 x i16> %shift) {
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; CHECK-LABEL: rotlv2_16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.2s, #15
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; CHECK-NEXT: neg v3.2s, v1.2s
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; CHECK-NEXT: movi d4, #0x00ffff0000ffff
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; CHECK-NEXT: and v3.8b, v3.8b, v2.8b
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; CHECK-NEXT: and v4.8b, v0.8b, v4.8b
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; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: neg v3.2s, v3.2s
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; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ushl v2.2s, v4.2s, v3.2s
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; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: ret
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%1 = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %vec2_16, <2 x i16> %vec2_16, <2 x i16> %shift)
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ret <2 x i16> %1
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}
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