61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
171 lines
5.9 KiB
LLVM
171 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel=1 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define fp128 @fabs_f128(fp128 %a) {
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; CHECK-SD-LABEL: fabs_f128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: str q0, [sp, #-16]!
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; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
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; CHECK-SD-NEXT: ldrb w8, [sp, #15]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #15]
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; CHECK-SD-NEXT: ldr q0, [sp], #16
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: fabs_f128:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
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; CHECK-GI-NEXT: and x8, x8, #0x7fffffffffffffff
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; CHECK-GI-NEXT: mov v0.d[1], x8
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; CHECK-GI-NEXT: ret
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entry:
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%c = call fp128 @llvm.fabs.f128(fp128 %a)
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ret fp128 %c
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}
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define <1 x fp128> @fabs_v1f128(<1 x fp128> %a) {
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; CHECK-SD-LABEL: fabs_v1f128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: str q0, [sp, #-16]!
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; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
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; CHECK-SD-NEXT: ldrb w8, [sp, #15]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #15]
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; CHECK-SD-NEXT: ldr q0, [sp], #16
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: fabs_v1f128:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
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; CHECK-GI-NEXT: and x8, x8, #0x7fffffffffffffff
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; CHECK-GI-NEXT: mov v0.d[1], x8
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <1 x fp128> @llvm.fabs.v1f128(<1 x fp128> %a)
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ret <1 x fp128> %c
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}
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define <2 x fp128> @fabs_v2f128(<2 x fp128> %a) {
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; CHECK-SD-LABEL: fabs_v2f128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]!
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; CHECK-SD-NEXT: .cfi_def_cfa_offset 32
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; CHECK-SD-NEXT: ldrb w8, [sp, #15]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #15]
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; CHECK-SD-NEXT: ldrb w8, [sp, #31]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #31]
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; CHECK-SD-NEXT: ldp q0, q1, [sp], #32
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: fabs_v2f128:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: mov x9, v1.d[1]
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; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
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; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
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; CHECK-GI-NEXT: and x8, x8, #0x7fffffffffffffff
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; CHECK-GI-NEXT: and x9, x9, #0x7fffffffffffffff
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; CHECK-GI-NEXT: mov v0.d[1], x8
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; CHECK-GI-NEXT: mov v1.d[1], x9
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <2 x fp128> @llvm.fabs.v2f128(<2 x fp128> %a)
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ret <2 x fp128> %c
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}
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define <3 x fp128> @fabs_v3f128(<3 x fp128> %a) {
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; CHECK-SD-LABEL: fabs_v3f128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: stp q0, q1, [sp, #-48]!
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; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
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; CHECK-SD-NEXT: ldrb w8, [sp, #15]
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; CHECK-SD-NEXT: str q2, [sp, #32]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #15]
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; CHECK-SD-NEXT: ldrb w8, [sp, #31]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #31]
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; CHECK-SD-NEXT: ldrb w8, [sp, #47]
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; CHECK-SD-NEXT: ldp q0, q1, [sp]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #47]
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; CHECK-SD-NEXT: ldr q2, [sp, #32]
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; CHECK-SD-NEXT: add sp, sp, #48
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: fabs_v3f128:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: mov x9, v1.d[1]
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; CHECK-GI-NEXT: mov x10, v2.d[1]
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; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
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; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
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; CHECK-GI-NEXT: mov v2.d[0], v2.d[0]
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; CHECK-GI-NEXT: and x8, x8, #0x7fffffffffffffff
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; CHECK-GI-NEXT: and x9, x9, #0x7fffffffffffffff
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; CHECK-GI-NEXT: and x10, x10, #0x7fffffffffffffff
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; CHECK-GI-NEXT: mov v0.d[1], x8
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; CHECK-GI-NEXT: mov v1.d[1], x9
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; CHECK-GI-NEXT: mov v2.d[1], x10
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <3 x fp128> @llvm.fabs.v3f128(<3 x fp128> %a)
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ret <3 x fp128> %c
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}
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define <4 x fp128> @fabs_v4f128(<4 x fp128> %a) {
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; CHECK-SD-LABEL: fabs_v4f128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: stp q0, q1, [sp, #-64]!
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; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
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; CHECK-SD-NEXT: ldrb w8, [sp, #15]
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; CHECK-SD-NEXT: stp q2, q3, [sp, #32]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #15]
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; CHECK-SD-NEXT: ldrb w8, [sp, #31]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #31]
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; CHECK-SD-NEXT: ldrb w8, [sp, #47]
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; CHECK-SD-NEXT: ldp q0, q1, [sp]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #47]
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; CHECK-SD-NEXT: ldrb w8, [sp, #63]
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; CHECK-SD-NEXT: and w8, w8, #0x7f
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; CHECK-SD-NEXT: strb w8, [sp, #63]
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; CHECK-SD-NEXT: ldp q2, q3, [sp, #32]
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; CHECK-SD-NEXT: add sp, sp, #64
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: fabs_v4f128:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: mov v7.d[0], v0.d[0]
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; CHECK-GI-NEXT: mov x9, v1.d[1]
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; CHECK-GI-NEXT: mov x10, v2.d[1]
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; CHECK-GI-NEXT: mov x11, v3.d[1]
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; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
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; CHECK-GI-NEXT: mov v2.d[0], v2.d[0]
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; CHECK-GI-NEXT: mov v3.d[0], v3.d[0]
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; CHECK-GI-NEXT: and x8, x8, #0x7fffffffffffffff
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; CHECK-GI-NEXT: mov v7.d[1], x8
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; CHECK-GI-NEXT: and x8, x9, #0x7fffffffffffffff
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; CHECK-GI-NEXT: and x9, x10, #0x7fffffffffffffff
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; CHECK-GI-NEXT: and x10, x11, #0x7fffffffffffffff
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; CHECK-GI-NEXT: mov v1.d[1], x8
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; CHECK-GI-NEXT: mov v2.d[1], x9
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; CHECK-GI-NEXT: mov v3.d[1], x10
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; CHECK-GI-NEXT: mov v0.16b, v7.16b
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <4 x fp128> @llvm.fabs.v4f128(<4 x fp128> %a)
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ret <4 x fp128> %c
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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