72901fe19e
Using the LSR or LSL aliases of UBFM can be faster on some CPUs, so it is worth changing 64 bit UBFM instructions, that are equivalent to 32 bit LSR/LSL operations, to 32 bit variants. This change folds the following patterns: * If `Imms == 31` and `Immr <= Imms`: `UBFMXri %0, Immr, Imms` -> `UBFMWri %0.sub_32, Immr, Imms` * If `Immr == Imms + 33`: `UBFMXri %0, Immr, Imms` -> `UBFMWri %0.sub_32, Immr - 32, Imms`
118 lines
3.3 KiB
LLVM
118 lines
3.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
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;
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; Test folding of the sign-/zero-extend into the load instruction.
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;
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; Unscaled
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define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i32
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; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: uxtb w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i8, ptr addrspace(256) %2
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i32
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; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: uxth w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i16, ptr addrspace(256) %2
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i64
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; CHECK: ldurb w[[REG:[0-9]+]], [x0, #-8]
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; CHECK: ubfx x0, x[[REG]], #0, #8
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i8, ptr addrspace(256) %2
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%4 = zext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i64
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; CHECK: ldurh w[[REG:[0-9]+]], [x0, #-8]
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; CHECK: ubfx x0, x[[REG]], #0, #16
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i16, ptr addrspace(256) %2
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%4 = zext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i32_to_i64
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; CHECK: ldur w[[REG:[0-9]+]], [x0, #-8]
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; CHECK: lsr w0, w[[REG]], #0
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i32, ptr addrspace(256) %2
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%4 = zext i32 %3 to i64
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ret i64 %4
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}
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define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i32
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; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxtb w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i8, ptr addrspace(256) %2
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%4 = sext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i16_to_i32
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; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxth w0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i16, ptr addrspace(256) %2
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%4 = sext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i64
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; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxtb x0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i8, ptr addrspace(256) %2
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%4 = sext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i16_to_i64
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; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxth x0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i16, ptr addrspace(256) %2
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%4 = sext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i32_to_i64
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; CHECK: ldur [[REG:w[0-9]+]], [x0, #-8]
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; CHECK: sxtw x0, [[REG]]
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to ptr addrspace(256)
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%3 = load i32, ptr addrspace(256) %2
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%4 = sext i32 %3 to i64
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ret i64 %4
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}
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