b4edd827e4
Previously, a separate load, zext and FMOV instruction was emitted. This patch adds a new TableGen pattern to avoid the unnecessary FMOV. A test is included in test/CodeGen/AArch64/load_u64_from_u32.ll
83 lines
2.2 KiB
LLVM
83 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
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; load zero-extended i32, bitcast to f64
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define double @_Z9load_u64_from_u32_testPj(ptr %n){
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; CHECK-LABEL: _Z9load_u64_from_u32_testPj:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, ptr %n, align 4
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%conv = zext i32 %0 to i64
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%1 = bitcast i64 %conv to double
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ret double %1
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}
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; load zero-extended i16, bitcast to f64
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define double @_Z9load_u64_from_u16_testPj(ptr %n){
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; CHECK-LABEL: _Z9load_u64_from_u16_testPj:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load i16, ptr %n, align 2
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%conv = zext i16 %0 to i64
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%1 = bitcast i64 %conv to double
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ret double %1
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}
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; load zero-extended i8, bitcast to f64
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define double @_Z16load_u64_from_u8Ph(ptr %n){
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; CHECK-LABEL: _Z16load_u64_from_u8Ph:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr b0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load i8, ptr %n, align 1
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%conv = zext i8 %0 to i64
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%1 = bitcast i64 %conv to double
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ret double %1
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}
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; load zero-extended i16, bitcast to f32
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define float @_Z17load_u32_from_u16Pt(ptr %n){
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; CHECK-LABEL: _Z17load_u32_from_u16Pt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load i16, ptr %n, align 2
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%conv = zext i16 %0 to i32
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%1 = bitcast i32 %conv to float
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ret float %1
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}
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; load zero-extended i8, bitcast to f32
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define float @_Z16load_u32_from_u8Ph(ptr %n){
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; CHECK-LABEL: _Z16load_u32_from_u8Ph:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr b0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load i8, ptr %n, align 1
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%conv = zext i8 %0 to i32
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%1 = bitcast i32 %conv to float
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ret float %1
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}
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; load zero-extended i8, bitcast to f16
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define half @_Z16load_u16_from_u8Ph(ptr %n){
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; CHECK-LABEL: _Z16load_u16_from_u8Ph:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr b0, [x0]
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%0 = load i8, ptr %n, align 1
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%conv = zext i8 %0 to i16
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%1 = bitcast i16 %conv to half
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ret half %1
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}
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