db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
146 lines
4.1 KiB
LLVM
146 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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; Check that under certain conditions we can factor out a rotate
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; from the following idioms:
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; (a*c0) >> s1 | (a*c1)
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; (a/c0) << s1 | (a/c1)
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; This targets cases where instcombine has folded a shl/srl/mul/udiv
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; with one of the shifts from the rotate idiom
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define i64 @ror_extract_shl(i64 %i) nounwind {
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; CHECK-LABEL: ror_extract_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x0, #3
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; CHECK-NEXT: ror x0, x8, #57
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; CHECK-NEXT: ret
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%lhs_mul = shl i64 %i, 3
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%rhs_mul = shl i64 %i, 10
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%lhs_shift = lshr i64 %lhs_mul, 57
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%out = or i64 %lhs_shift, %rhs_mul
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ret i64 %out
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}
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define i32 @ror_extract_shrl(i32 %i) nounwind {
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; CHECK-LABEL: ror_extract_shrl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #3
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; CHECK-NEXT: ror w0, w8, #4
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; CHECK-NEXT: ret
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%lhs_div = lshr i32 %i, 7
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%rhs_div = lshr i32 %i, 3
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%rhs_shift = shl i32 %rhs_div, 28
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%out = or i32 %lhs_div, %rhs_shift
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ret i32 %out
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}
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define i32 @ror_extract_mul(i32 %i) nounwind {
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; CHECK-LABEL: ror_extract_mul:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, w0, lsl #3
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; CHECK-NEXT: ror w0, w8, #25
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; CHECK-NEXT: ret
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%lhs_mul = mul i32 %i, 9
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%rhs_mul = mul i32 %i, 1152
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%lhs_shift = lshr i32 %lhs_mul, 25
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%out = or i32 %lhs_shift, %rhs_mul
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ret i32 %out
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}
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define i64 @ror_extract_udiv(i64 %i) nounwind {
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; CHECK-LABEL: ror_extract_udiv:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
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; CHECK-NEXT: movk x8, #43691
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; CHECK-NEXT: umulh x8, x0, x8
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; CHECK-NEXT: lsr x8, x8, #1
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; CHECK-NEXT: ror x0, x8, #4
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; CHECK-NEXT: ret
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%lhs_div = udiv i64 %i, 3
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%rhs_div = udiv i64 %i, 48
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%lhs_shift = shl i64 %lhs_div, 60
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%out = or i64 %lhs_shift, %rhs_div
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ret i64 %out
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}
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define i64 @ror_extract_mul_with_mask(i64 %i) nounwind {
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; CHECK-LABEL: ror_extract_mul_with_mask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, x0, lsl #3
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; CHECK-NEXT: ror x8, x8, #57
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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%lhs_mul = mul i64 %i, 1152
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%rhs_mul = mul i64 %i, 9
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%lhs_and = and i64 %lhs_mul, 160
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%rhs_shift = lshr i64 %rhs_mul, 57
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%out = or i64 %lhs_and, %rhs_shift
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ret i64 %out
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}
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; Result would undershift
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define i64 @no_extract_shl(i64 %i) nounwind {
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; CHECK-LABEL: no_extract_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x0, #10
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; CHECK-NEXT: bfxil x8, x0, #52, #7
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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%lhs_mul = shl i64 %i, 5
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%rhs_mul = shl i64 %i, 10
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%lhs_shift = lshr i64 %lhs_mul, 57
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%out = or i64 %lhs_shift, %rhs_mul
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ret i64 %out
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}
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; Result would overshift
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define i32 @no_extract_shrl(i32 %i) nounwind {
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; CHECK-LABEL: no_extract_shrl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #3
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; CHECK-NEXT: lsr w0, w0, #9
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; CHECK-NEXT: bfi w0, w8, #28, #4
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; CHECK-NEXT: ret
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%lhs_div = lshr i32 %i, 3
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%rhs_div = lshr i32 %i, 9
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%lhs_shift = shl i32 %lhs_div, 28
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%out = or i32 %lhs_shift, %rhs_div
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ret i32 %out
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}
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; Can factor 128 from 2304, but result is 18 instead of 9
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define i64 @no_extract_mul(i64 %i) nounwind {
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; CHECK-LABEL: no_extract_mul:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, x0, lsl #3
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; CHECK-NEXT: lsr x9, x8, #57
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; CHECK-NEXT: orr x0, x9, x8, lsl #8
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; CHECK-NEXT: ret
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%lhs_mul = mul i64 %i, 2304
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%rhs_mul = mul i64 %i, 9
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%rhs_shift = lshr i64 %rhs_mul, 57
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%out = or i64 %lhs_mul, %rhs_shift
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ret i64 %out
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}
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; Can't evenly factor 16 from 49
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define i32 @no_extract_udiv(i32 %i) nounwind {
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; CHECK-LABEL: no_extract_udiv:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691 // =0xaaab
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; CHECK-NEXT: mov w9, #33437 // =0x829d
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: movk w9, #21399, lsl #16
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; CHECK-NEXT: umull x8, w0, w8
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; CHECK-NEXT: umull x9, w0, w9
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; CHECK-NEXT: lsr x8, x8, #33
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; CHECK-NEXT: lsr x9, x9, #32
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; CHECK-NEXT: extr w0, w8, w9, #4
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; CHECK-NEXT: ret
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%lhs_div = udiv i32 %i, 3
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%rhs_div = udiv i32 %i, 49
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%lhs_shift = shl i32 %lhs_div, 28
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%out = or i32 %lhs_shift, %rhs_div
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ret i32 %out
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}
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