c649fd34e9
This patch adds a new code transformation to the `MachineSink` pass, that tries to sink copies of an instruction, when the copies can be folded into the addressing modes of load/store instructions, or replace another instruction (currently, copies into a hard register). The criteria for performing the transformation is that: * the register pressure at the sink destination block must not exceed the register pressure limits * the latency and throughput of the load/store or the copy must not deteriorate * the original instruction must be deleted Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D152828
20 lines
506 B
LLVM
20 lines
506 B
LLVM
; RUN: llc -mtriple arm64-ios- -aarch64-enable-sink-fold=true %s -o - | FileCheck %s
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; Check the -8 constant is shrunk if there are multiple users of the AND instruction.
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; CHECK-LABEL: _test:
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; CHECK: and x19, x0, #0xfffffff8
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; CHECK-NEXT: mov x0, x19
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; CHECK-NEXT: bl _user
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; CHECK: add x0, x19, #10
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define i64 @test(i32 %a) {
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%ext = zext i32 %a to i64
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%v1 = and i64 %ext, -8
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%v2 = add i64 %v1, 10
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call void @user(i64 %v1)
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ret i64 %v2
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}
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declare void @user(i64)
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