ef395a492a
This is re-working of #74460, which adds a soft-float ABI for AArch64. That was reverted because it causes errors when building the linux and fuchsia kernels. The problem is that GCC's implementation of the ABI compatibility checks when using the hard-float ABI on a target without FP registers does it's checks after optimisation. The previous version of this patch reported errors for all uses of floating-point types, which is stricter than what GCC does in practice. This changes two things compared to the first version: * Only check the types of function arguments and returns, not the types of other values. This is more relaxed than GCC, while still guaranteeing ABI compatibility. * Move the check from Sema to CodeGen, so that inline functions are only checked if they are actually used. There are some cases in the linux kernel which depend on this behaviour of GCC.
162 lines
5.2 KiB
LLVM
162 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple aarch64-none-eabi < %s -mattr=-fp-armv8 | FileCheck %s
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; See also clang/test/CodeGen/aarch64-soft-float-abi.c, which tests the clang
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; parts of the soft-float ABI.
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; FP types up to 64-bit are passed in a general purpose register.
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define half @test0(half %a, half %b) {
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; CHECK-LABEL: test0:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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entry:
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ret half %b
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}
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define bfloat @test1(i32 %a, bfloat %b) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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entry:
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ret bfloat %b
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}
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define float @test2(i64 %a, float %b) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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entry:
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ret float %b
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}
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define double @test3(half %a, double %b) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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entry:
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ret double %b
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}
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; fp128 is passed in a pair of GPRs.
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define fp128 @test4(fp128 %a, fp128 %b) {
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x1, x3
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; CHECK-NEXT: mov x0, x2
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; CHECK-NEXT: ret
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entry:
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ret fp128 %b
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}
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; fp128 is passed in an aligned pair of GPRs, leaving one register unused is
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; necessary.
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define fp128 @test5(float %a, fp128 %b) {
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x1, x3
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; CHECK-NEXT: mov x0, x2
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; CHECK-NEXT: ret
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entry:
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ret fp128 %b
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}
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; If the alignment of an fp128 leaves a register unused, it remains unused even
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; if a later argument could fit in it.
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define i64 @test6(i64 %a, fp128 %b, i64 %c) {
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x0, x4
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; CHECK-NEXT: ret
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entry:
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ret i64 %c
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}
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; HFAs are all bit-casted to integer types in the frontend when using the
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; soft-float ABI, so they get passed in the same way as non-homeogeneous
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; aggregates. The IR is identical to the equivalent integer types, so nothing
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; to test here.
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; The PCS for vector and HVA types is not defined by the soft-float ABI because
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; these types are only defined by the ACLE when vector hardware is available,
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; so nothing to test here.
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; The front-end generates IR for va_arg which always reads from the integer
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; register save area, and never the floating-point register save area. The
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; layout of the va_list type remains the same, the floating-point related
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; fields are unused. The only change needed in the backend is in va_start, to
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; not attempt to save the floating-point registers or set the FP fields in the
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; va_list.
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%struct.__va_list = type { ptr, ptr, ptr, i32, i32 }
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declare void @llvm.va_start(ptr)
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define double @test20(i32 %a, ...) {
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; CHECK-LABEL: test20:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #96
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; CHECK-NEXT: .cfi_def_cfa_offset 96
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; CHECK-NEXT: mov w8, #-56 // =0xffffffc8
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; CHECK-NEXT: add x10, sp, #8
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; CHECK-NEXT: add x9, sp, #96
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; CHECK-NEXT: str x8, [sp, #88]
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; CHECK-NEXT: add x10, x10, #56
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; CHECK-NEXT: ldrsw x8, [sp, #88]
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; CHECK-NEXT: stp x1, x2, [sp, #8]
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; CHECK-NEXT: stp x3, x4, [sp, #24]
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; CHECK-NEXT: stp x5, x6, [sp, #40]
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; CHECK-NEXT: stp x7, x9, [sp, #56]
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; CHECK-NEXT: str x10, [sp, #72]
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; CHECK-NEXT: tbz w8, #31, .LBB7_3
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; CHECK-NEXT: // %bb.1: // %vaarg.maybe_reg
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; CHECK-NEXT: add w9, w8, #8
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; CHECK-NEXT: cmn w8, #8
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; CHECK-NEXT: str w9, [sp, #88]
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; CHECK-NEXT: b.gt .LBB7_3
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; CHECK-NEXT: // %bb.2: // %vaarg.in_reg
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; CHECK-NEXT: ldr x9, [sp, #72]
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; CHECK-NEXT: add x8, x9, x8
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; CHECK-NEXT: b .LBB7_4
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; CHECK-NEXT: .LBB7_3: // %vaarg.on_stack
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; CHECK-NEXT: ldr x8, [sp, #64]
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; CHECK-NEXT: add x9, x8, #8
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; CHECK-NEXT: str x9, [sp, #64]
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; CHECK-NEXT: .LBB7_4: // %vaarg.end
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; CHECK-NEXT: ldr x0, [x8]
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; CHECK-NEXT: add sp, sp, #96
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; CHECK-NEXT: ret
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entry:
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%vl = alloca %struct.__va_list, align 8
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call void @llvm.va_start(ptr nonnull %vl)
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%gr_offs_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 3
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%gr_offs = load i32, ptr %gr_offs_p, align 8
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%0 = icmp sgt i32 %gr_offs, -1
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br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg
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vaarg.maybe_reg: ; preds = %entry
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%new_reg_offs = add nsw i32 %gr_offs, 8
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store i32 %new_reg_offs, ptr %gr_offs_p, align 8
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%inreg = icmp slt i32 %gr_offs, -7
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br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
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vaarg.in_reg: ; preds = %vaarg.maybe_reg
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%reg_top_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 1
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%reg_top = load ptr, ptr %reg_top_p, align 8
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%1 = sext i32 %gr_offs to i64
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%2 = getelementptr inbounds i8, ptr %reg_top, i64 %1
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br label %vaarg.end
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vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry
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%stack = load ptr, ptr %vl, align 8
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%new_stack = getelementptr inbounds i8, ptr %stack, i64 8
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store ptr %new_stack, ptr %vl, align 8
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br label %vaarg.end
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vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
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%vaargs.addr = phi ptr [ %2, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
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%3 = load double, ptr %vaargs.addr, align 8
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ret double %3
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}
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