58a88001f3
This fixes the handling of subregister extract copies. This will allow AMDGPU to remove its implementation of shouldRewriteCopySrc, which exists as a 10 year old workaround to this bug. peephole-opt-fold-reg-sequence-subreg.mir will show the expected improvement once the custom implementation is removed. The copy coalescing processing here is overly abstracted from what's actually happening. Previously when visiting coalescable copy-like instructions, we would parse the sources one at a time and then pass the def of the root instruction into findNextSource. This means that the first thing the new ValueTracker constructed would do is getVRegDef to find the instruction we are currently processing. This adds an unnecessary step, placing a useless entry in the RewriteMap, and required skipping the no-op case where getNewSource would return the original source operand. This was a problem since in the case of a subregister extract, shouldRewriteCopySource would always say that it is useful to rewrite and the use-def chain walk would abort, returning the original operand. Move the process to start looking at the source operand to begin with. This does not fix the confused handling in the uncoalescable copy case which is proving to be more difficult. Some currently handled cases have multiple defs from a single source, and other handled cases have 0 input operands. It would be simpler if this was implemented with isCopyLikeInstr, rather than guessing at the operand structure as it does now. There are some improvements and some regressions. The regressions appear to be downstream issues for the most part. One of the uglier regressions is in PPC, where a sequence of insert_subrgs is used to build registers. I opened #125502 to use reg_sequence instead, which may help. The worst regression is an absurd SPARC testcase using a <251 x fp128>, which uses a very long chain of insert_subregs. We need improved subregister handling locally in PeepholeOptimizer, and other pasess like MachineCSE to fix some of the other regressions. We should handle subregister composes and folding more indexes into insert_subreg and reg_sequence.
447 lines
13 KiB
LLVM
447 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; Test we can code generater patterns of the form:
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; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
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; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0
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;
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; NOTE: Currently shufflevector does not support scalable vectors so it cannot
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; be used to model the above operations. Instead these tests rely on knowing
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; how fixed length operation are lowered to scalable ones, with multiple blocks
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; ensuring insert/extract sequences are not folded away.
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target triple = "aarch64-unknown-linux-gnu"
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define void @subvector_v8i16(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i16>, ptr %in
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br label %bb1
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bb1:
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store <8 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v16i16(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl16
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x i16>, ptr %in
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br label %bb1
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bb1:
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store <16 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v32i16(ptr %in, ptr %out) #0 {
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; VBITS_GE_256-LABEL: subvector_v32i16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: subvector_v32i16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <32 x i16>, ptr %in
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br label %bb1
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bb1:
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store <32 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v64i16(ptr %in, ptr %out) vscale_range(8,0) #0 {
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; CHECK-LABEL: subvector_v64i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl64
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <64 x i16>, ptr %in
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br label %bb1
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bb1:
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store <64 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v8i32(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i32>, ptr %in
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br label %bb1
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bb1:
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store <8 x i32> %a, ptr %out
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ret void
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}
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define void @subvector_v16i32(ptr %in, ptr %out) #0 {
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; VBITS_GE_256-LABEL: subvector_v16i32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1, x8, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: subvector_v16i32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <16 x i32>, ptr %in
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br label %bb1
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bb1:
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store <16 x i32> %a, ptr %out
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ret void
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}
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define void @subvector_v32i32(ptr %in, ptr %out) vscale_range(8,0) #0 {
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; CHECK-LABEL: subvector_v32i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <32 x i32>, ptr %in
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br label %bb1
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bb1:
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store <32 x i32> %a, ptr %out
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ret void
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}
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define void @subvector_v64i32(ptr %in, ptr %out) vscale_range(16,0) #0 {
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; CHECK-LABEL: subvector_v64i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl64
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <64 x i32>, ptr %in
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br label %bb1
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bb1:
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store <64 x i32> %a, ptr %out
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ret void
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}
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define void @subvector_v8i64(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: mov x8, #4 // =0x4
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i64>, ptr %in
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br label %bb1
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bb1:
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store <8 x i64> %a, ptr %out
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ret void
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}
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define void @subvector_v16i64(ptr %in, ptr %out) vscale_range(8,0) #0 {
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; CHECK-LABEL: subvector_v16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl16
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x i64>, ptr %in
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br label %bb1
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bb1:
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store <16 x i64> %a, ptr %out
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ret void
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}
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define void @subvector_v32i64(ptr %in, ptr %out) vscale_range(16,0) #0 {
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; CHECK-LABEL: subvector_v32i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl32
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <32 x i64>, ptr %in
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br label %bb1
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bb1:
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store <32 x i64> %a, ptr %out
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ret void
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}
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define void @subvector_v8f16(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x half>, ptr %in
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br label %bb1
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bb1:
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store <8 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v16f16(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl16
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x half>, ptr %in
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br label %bb1
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bb1:
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store <16 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v32f16(ptr %in, ptr %out) #0 {
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; VBITS_GE_256-LABEL: subvector_v32f16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: subvector_v32f16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <32 x half>, ptr %in
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br label %bb1
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bb1:
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store <32 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v64f16(ptr %in, ptr %out) vscale_range(8,0) #0 {
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; CHECK-LABEL: subvector_v64f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl64
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <64 x half>, ptr %in
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br label %bb1
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bb1:
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store <64 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v8f32(ptr %in, ptr %out) vscale_range(2,0) #0 {
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; CHECK-LABEL: subvector_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x float>, ptr %in
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br label %bb1
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bb1:
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store <8 x float> %a, ptr %out
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ret void
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}
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define void @subvector_v16f32(ptr %in, ptr %out) #0 {
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; VBITS_GE_256-LABEL: subvector_v16f32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1, x8, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: subvector_v16f32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <16 x float>, ptr %in
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br label %bb1
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bb1:
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store <16 x float> %a, ptr %out
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ret void
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}
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define void @subvector_v32f32(ptr %in, ptr %out) vscale_range(8,0) #0 {
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; CHECK-LABEL: subvector_v32f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <32 x float>, ptr %in
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br label %bb1
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bb1:
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store <32 x float> %a, ptr %out
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ret void
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}
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define void @subvector_v64f32(ptr %in, ptr %out) vscale_range(16,0) #0 {
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; CHECK-LABEL: subvector_v64f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl64
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <64 x float>, ptr %in
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br label %bb1
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bb1:
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store <64 x float> %a, ptr %out
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ret void
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}
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define void @subvector_v8f64(ptr %in, ptr %out) #0 {
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; VBITS_GE_256-LABEL: subvector_v8f64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1, x8, lsl #3]
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: subvector_v8f64:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <8 x double>, ptr %in
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br label %bb1
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bb1:
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store <8 x double> %a, ptr %out
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ret void
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}
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define void @subvector_v16f64(ptr %in, ptr %out) vscale_range(8,0) #0 {
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; CHECK-LABEL: subvector_v16f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl16
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x double>, ptr %in
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br label %bb1
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bb1:
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store <16 x double> %a, ptr %out
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ret void
|
|
}
|
|
|
|
define void @subvector_v32f64(ptr %in, ptr %out) vscale_range(16,0) #0 {
|
|
; CHECK-LABEL: subvector_v32f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl32
|
|
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
|
|
; CHECK-NEXT: st1d { z0.d }, p0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%a = load <32 x double>, ptr %in
|
|
br label %bb1
|
|
|
|
bb1:
|
|
store <32 x double> %a, ptr %out
|
|
ret void
|
|
}
|
|
|
|
define <8 x i1> @no_warn_dropped_scalable(ptr %in) #0 {
|
|
; CHECK-LABEL: no_warn_dropped_scalable:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl8
|
|
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
|
|
; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #0
|
|
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x i32>, ptr %in
|
|
br label %bb1
|
|
|
|
bb1:
|
|
%cond = icmp sgt <8 x i32> %a, zeroinitializer
|
|
ret <8 x i1> %cond
|
|
}
|
|
|
|
; binop(insert_subvec(a), insert_subvec(b)) -> insert_subvec(binop(a,b)) like
|
|
; combines remove redundant subvector operations. This test ensures it's not
|
|
; performed when the input idiom is the result of operation legalisation. When
|
|
; not prevented the test triggers infinite combine->legalise->combine->...
|
|
define void @no_subvector_binop_hang(ptr %in, ptr %out, i1 %cond) #0 {
|
|
; CHECK-LABEL: no_subvector_binop_hang:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: tbz w2, #0, .LBB23_2
|
|
; CHECK-NEXT: // %bb.1: // %bb.1
|
|
; CHECK-NEXT: ptrue p0.s, vl8
|
|
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: st1w { z0.s }, p0, [x1]
|
|
; CHECK-NEXT: .LBB23_2: // %bb.2
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x i32>, ptr %in
|
|
%b = load <8 x i32>, ptr %out
|
|
br i1 %cond, label %bb.1, label %bb.2
|
|
|
|
bb.1:
|
|
%or = or <8 x i32> %a, %b
|
|
store <8 x i32> %or, ptr %out
|
|
br label %bb.2
|
|
|
|
bb.2:
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|