fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
178 lines
5.4 KiB
LLVM
178 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
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define amdgpu_kernel void @s_clear_msb(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_clear_msb:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = and i32 %in, 2147483647
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_set_msb(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_set_msb:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_or_b32 s4, s6, 0x80000000
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = or i32 %in, 2147483648
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_clear_lsb(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_clear_lsb:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_and_b32 s4, s6, -2
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = and i32 %in, 4294967294
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_set_lsb(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_set_lsb:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_or_b32 s4, s6, 1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = or i32 %in, 1
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_clear_midbit(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_clear_midbit:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_and_b32 s4, s6, 0xfffffeff
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = and i32 %in, 4294967039
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_set_midbit(ptr addrspace(1) %out, i32 %in) {
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; SI-LABEL: s_set_midbit:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_or_b32 s4, s6, 0x100
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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%x = or i32 %in, 256
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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@gv = external addrspace(1) global i32
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; Make sure there's no verifier error with an undef source.
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define void @bitset_verifier_error_freeze_poison() local_unnamed_addr #0 {
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; SI-LABEL: bitset_verifier_error_freeze_poison:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_getpc_b64 s[4:5]
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; SI-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4
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; SI-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12
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; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_and_b32 s8, s4, 0x7fffffff
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; SI-NEXT: v_mov_b32_e32 v0, s8
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt expcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, 0x3f7fbe77
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; SI-NEXT: v_cmp_ge_f32_e64 s[4:5], |s4|, v0
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; SI-NEXT: s_and_b64 vcc, exec, s[4:5]
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; SI-NEXT: s_cbranch_vccnz .LBB6_2
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; SI-NEXT: ; %bb.1: ; %bb5
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; SI-NEXT: .LBB6_2: ; %bb6
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bb:
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%undef0 = freeze float poison
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%i = call float @llvm.fabs.f32(float %undef0) #0
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%i1 = bitcast float %i to i32
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store i32 %i1, ptr addrspace(1) @gv
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br label %bb2
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bb2:
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%undef1 = freeze float poison
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%i3 = call float @llvm.fabs.f32(float %undef1) #0
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%i4 = fcmp fast ult float %i3, 0x3FEFF7CEE0000000
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br i1 %i4, label %bb5, label %bb6
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bb5:
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unreachable
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bb6:
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unreachable
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}
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define void @bitset_verifier_error_poison() local_unnamed_addr #0 {
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; SI-LABEL: bitset_verifier_error_poison:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_cbranch_scc1 .LBB7_2
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; SI-NEXT: ; %bb.1: ; %bb5
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; SI-NEXT: .LBB7_2: ; %bb6
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bb:
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%i = call float @llvm.fabs.f32(float poison) #0
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%i1 = bitcast float %i to i32
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store i32 %i1, ptr addrspace(1) @gv
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br label %bb2
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bb2:
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%i3 = call float @llvm.fabs.f32(float poison) #0
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%i4 = fcmp fast ult float %i3, 0x3FEFF7CEE0000000
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br i1 %i4, label %bb5, label %bb6
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bb5:
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unreachable
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bb6:
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unreachable
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}
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declare float @llvm.fabs.f32(float) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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