5feb32ba92
This patch is intended to be the first of a series with end goal to adapt atomic optimizer pass to support i64 and f64 operations (along with removing all unnecessary bitcasts). This legalizes 64 bit readlane, writelane and readfirstlane ops pre-ISel --------- Co-authored-by: vikramRH <vikhegde@amd.com>
89 lines
4.1 KiB
LLVM
89 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -mtriple=amdgcn-- -mcpu=gfx908 -passes="amdgpu-atomic-optimizer,verify<domtree>" %s -S -o - | FileCheck %s
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; Check we're properly adding an edge from ComputeEnd to the "End" block added by
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; SplitBlockAndInsertIfThen
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;
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; If the edge is not added, domtree verification will fail.
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declare i32 @quux()
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define amdgpu_kernel void @ham(ptr addrspace(4) %arg) {
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; CHECK-LABEL: define amdgpu_kernel void @ham(
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; CHECK-SAME: ptr addrspace(4) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @quux()
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; CHECK-NEXT: [[ICMP:%.*]] = icmp eq i32 [[CALL]], 0
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; CHECK-NEXT: br i1 [[ICMP]], label [[BB1:%.*]], label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 @quux()
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb3:
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; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[CALL2]], [[BB1]] ], [ [[CALL]], [[BB:%.*]] ]
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; CHECK-NEXT: br label [[BB4:%.*]]
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; CHECK: bb4:
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; CHECK-NEXT: [[CALL5:%.*]] = tail call i32 @quux()
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; CHECK-NEXT: [[ICMP6:%.*]] = icmp eq i32 [[CALL5]], 0
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; CHECK-NEXT: br i1 [[ICMP6]], label [[BB8:%.*]], label [[BB7:%.*]]
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; CHECK: bb7:
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; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG]], align 8
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; CHECK-NEXT: [[ADDRSPACECAST:%.*]] = addrspacecast ptr [[LOAD]] to ptr addrspace(1)
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; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
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; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
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; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
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; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
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; CHECK-NEXT: br label [[COMPUTELOOP:%.*]]
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; CHECK: 7:
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; CHECK-NEXT: [[TMP8:%.*]] = atomicrmw add ptr addrspace(1) [[ADDRSPACECAST]], i32 [[TMP13:%.*]] syncscope("agent-one-as") monotonic, align 4
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; CHECK-NEXT: br label [[TMP9:%.*]]
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; CHECK: 9:
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; CHECK-NEXT: br label [[BB8]]
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; CHECK: bb8:
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; CHECK-NEXT: br label [[BB4]]
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; CHECK: ComputeLoop:
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; CHECK-NEXT: [[ACCUMULATOR:%.*]] = phi i32 [ 0, [[BB7]] ], [ [[TMP13]], [[COMPUTELOOP]] ]
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; CHECK-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP6]], [[BB7]] ], [ [[TMP16:%.*]], [[COMPUTELOOP]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
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; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i32
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; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[PHI]], i32 [[TMP11]])
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; CHECK-NEXT: [[TMP13]] = add i32 [[ACCUMULATOR]], [[TMP12]]
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; CHECK-NEXT: [[TMP14:%.*]] = shl i64 1, [[TMP10]]
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; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP14]], -1
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; CHECK-NEXT: [[TMP16]] = and i64 [[ACTIVEBITS]], [[TMP15]]
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[TMP16]], 0
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; CHECK-NEXT: br i1 [[TMP17]], label [[COMPUTEEND:%.*]], label [[COMPUTELOOP]]
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; CHECK: ComputeEnd:
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; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: br i1 [[TMP18]], label [[TMP7:%.*]], label [[TMP9]]
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;
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bb:
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%call = tail call i32 @quux()
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%icmp = icmp eq i32 %call, 0
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br i1 %icmp, label %bb1, label %bb3
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bb1: ; preds = %bb
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%call2 = tail call i32 @quux()
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br label %bb3
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bb3: ; preds = %bb1, %bb
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%phi = phi i32 [ %call2, %bb1 ], [ %call, %bb ]
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br label %bb4
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bb4: ; preds = %bb8, %bb3
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%call5 = tail call i32 @quux()
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%icmp6 = icmp eq i32 %call5, 0
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br i1 %icmp6, label %bb8, label %bb7
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bb7: ; preds = %bb4
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%load = load ptr, ptr addrspace(4) %arg, align 8
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%addrspacecast = addrspacecast ptr %load to ptr addrspace(1)
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%atomicrmw = atomicrmw add ptr addrspace(1) %addrspacecast, i32 %phi syncscope("agent-one-as") monotonic, align 4
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br label %bb8
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bb8: ; preds = %bb7, %bb4
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br label %bb4
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}
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