578741b5e8
Currently, we use `AAAMDWavesPerEU` to iteratively update values based on attributes from the associated function, potentially propagating user-annotated values, along with `AAAMDFlatWorkGroupSize`. Similarly, we have `AAAMDFlatWorkGroupSize`. However, since the value calculated through the flat workgroup size always dominates the user annotation (i.e., the attribute), running `AAAMDWavesPerEU` iteratively is unnecessary if no user-annotated value exists. This PR completely rewrites how the `amdgpu-waves-per-eu` attribute is handled in `AMDGPUAttributor`. The key changes are as follows: - `AAAMDFlatWorkGroupSize` remains unchanged. - `AAAMDWavesPerEU` now only propagates user-annotated values. - A new function is added to check and update `amdgpu-waves-per-eu` based on the following rules: - No waves per eu, no flat workgroup size: Assume a flat workgroup size of `1,1024` and compute waves per eu based on this. - No waves per eu, flat workgroup size exists: Use the provided flat workgroup size to compute waves-per-eu. - Waves per eu exists, no flat workgroup size: This is a tricky case. In this PR, we assume a flat workgroup size of `1,1024`, but this can be adjusted if a different approach is preferred. Alternatively, we could directly use the user-annotated value. - Both waves per eu and flat workgroup size exist: If there’s a conflict, the value derived from the flat workgroup size takes precedence over waves per eu. This PR also updates the logic for merging two waves per eu pairs. The current implementation, which uses `clampStateAndIndicateChange` to compute a union, might not be ideal. If we think from ensure proper resource allocation perspective, for instance, if one pair specifies a minimum of 2 waves per eu, and another specifies a minimum of 4, we should guarantee that 4 waves per eu can be supported, as failing to do so could result in excessive resource allocation per wave. A similar principle applies to the upper bound. Thus, the PR uses the following approach for merging two pairs, `lo_a,up_a` and `lo_b,up_b`: `max(lo_a, lo_b), max(up_a, up_b)`. This ensures that resource allocation adheres to the stricter constraints from both inputs. Fix #123092.
156 lines
8.2 KiB
LLVM
156 lines
8.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals all --version 5
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-attributor < %s | FileCheck -check-prefixes=GFX9 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=amdgpu-attributor < %s | FileCheck -check-prefixes=GFX10 %s
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;
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; None of these functions should have the attribute amdgpu-no-flat-scratch-init. In these tests
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; we manually set the attribute for the functions. The purpose is to test how the amdgpu-attributor pass
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; handles this situation.
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;
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;; tests of addrspacecast
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define void @with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
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; GFX9-LABEL: define void @with_private_to_flat_addrspacecast(
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; GFX9-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
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; GFX9-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr
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; GFX9-NEXT: store volatile i32 0, ptr [[STOF]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define void @with_private_to_flat_addrspacecast(
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; GFX10-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
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; GFX10-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr
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; GFX10-NEXT: store volatile i32 0, ptr [[STOF]], align 4
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; GFX10-NEXT: ret void
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;
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%stof = addrspacecast ptr addrspace(5) %ptr to ptr
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store volatile i32 0, ptr %stof
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ret void
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}
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define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(ptr addrspace(5) %ptr) #0 {
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; GFX9-LABEL: define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(
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; GFX9-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr
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; GFX9-NEXT: store volatile i32 0, ptr [[STOF]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(
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; GFX10-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr
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; GFX10-NEXT: store volatile i32 0, ptr [[STOF]], align 4
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; GFX10-NEXT: ret void
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;
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%stof = addrspacecast ptr addrspace(5) %ptr to ptr
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store volatile i32 0, ptr %stof
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ret void
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}
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define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
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; GFX9-LABEL: define void @call_with_private_to_flat_addrspacecast(
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; GFX9-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: call void @with_private_to_flat_addrspacecast(ptr addrspace(5) [[PTR]])
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define void @call_with_private_to_flat_addrspacecast(
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; GFX10-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: call void @with_private_to_flat_addrspacecast(ptr addrspace(5) [[PTR]])
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; GFX10-NEXT: ret void
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;
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call void @with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr)
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ret void
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}
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define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(ptr addrspace(5) %ptr) #0 {
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; GFX9-LABEL: define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(
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; GFX9-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: call void @with_private_to_flat_addrspacecast(ptr addrspace(5) [[PTR]])
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(
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; GFX10-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: call void @with_private_to_flat_addrspacecast(ptr addrspace(5) [[PTR]])
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; GFX10-NEXT: ret void
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;
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call void @with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr)
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ret void
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}
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;; tests of addrspacecast in a constant
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define amdgpu_kernel void @private_constant_expression_use(ptr addrspace(1) nocapture %out) #0 {
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; GFX9-LABEL: define amdgpu_kernel void @private_constant_expression_use(
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; GFX9-SAME: ptr addrspace(1) captures(none) [[OUT:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: store volatile ptr addrspacecast (ptr addrspace(5) inttoptr (i32 123 to ptr addrspace(5)) to ptr), ptr addrspace(1) [[OUT]], align 8
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define amdgpu_kernel void @private_constant_expression_use(
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; GFX10-SAME: ptr addrspace(1) captures(none) [[OUT:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: store volatile ptr addrspacecast (ptr addrspace(5) inttoptr (i32 123 to ptr addrspace(5)) to ptr), ptr addrspace(1) [[OUT]], align 8
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; GFX10-NEXT: ret void
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;
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store volatile ptr addrspacecast (ptr addrspace(5) inttoptr (i32 123 to ptr addrspace(5)) to ptr), ptr addrspace(1) %out, align 8
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ret void
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}
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;; tests of intrinsics
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define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) #0 {
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; GFX9-LABEL: define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(
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; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]])
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; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(
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; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]])
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; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4
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; GFX10-NEXT: ret void
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;
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%1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr)
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store volatile i32 7, ptr %1, align 4
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ret void
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}
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define void @calls_intrin_ascast(ptr addrspace(3) %ptr) #0 {
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; GFX9-LABEL: define void @calls_intrin_ascast(
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; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]])
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; GFX9-NEXT: store volatile i32 7, ptr [[TMP1]], align 4
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define void @calls_intrin_ascast(
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; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: [[TMP1:%.*]] = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) [[PTR]])
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; GFX10-NEXT: store volatile i32 7, ptr [[TMP1]], align 4
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; GFX10-NEXT: ret void
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;
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%1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr)
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store volatile i32 7, ptr %1, align 4
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ret void
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}
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define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) #0 {
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; GFX9-LABEL: define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(
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; GFX9-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX9-NEXT: call void @calls_intrin_ascast(ptr addrspace(3) [[PTR]])
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; GFX9-NEXT: ret void
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;
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; GFX10-LABEL: define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(
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; GFX10-SAME: ptr addrspace(3) [[PTR:%.*]]) #[[ATTR0]] {
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; GFX10-NEXT: call void @calls_intrin_ascast(ptr addrspace(3) [[PTR]])
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; GFX10-NEXT: ret void
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;
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call void @calls_intrin_ascast(ptr addrspace(3) %ptr)
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ret void
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}
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attributes #0 = { "amdgpu-no-flat-scratch-init" }
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;.
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; GFX9: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "target-cpu"="gfx900" "uniform-work-group-size"="false" }
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; GFX9: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx900" }
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;.
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; GFX10: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="8,20" "target-cpu"="gfx1010" "uniform-work-group-size"="false" }
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; GFX10: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx1010" }
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;.
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