578741b5e8
Currently, we use `AAAMDWavesPerEU` to iteratively update values based on attributes from the associated function, potentially propagating user-annotated values, along with `AAAMDFlatWorkGroupSize`. Similarly, we have `AAAMDFlatWorkGroupSize`. However, since the value calculated through the flat workgroup size always dominates the user annotation (i.e., the attribute), running `AAAMDWavesPerEU` iteratively is unnecessary if no user-annotated value exists. This PR completely rewrites how the `amdgpu-waves-per-eu` attribute is handled in `AMDGPUAttributor`. The key changes are as follows: - `AAAMDFlatWorkGroupSize` remains unchanged. - `AAAMDWavesPerEU` now only propagates user-annotated values. - A new function is added to check and update `amdgpu-waves-per-eu` based on the following rules: - No waves per eu, no flat workgroup size: Assume a flat workgroup size of `1,1024` and compute waves per eu based on this. - No waves per eu, flat workgroup size exists: Use the provided flat workgroup size to compute waves-per-eu. - Waves per eu exists, no flat workgroup size: This is a tricky case. In this PR, we assume a flat workgroup size of `1,1024`, but this can be adjusted if a different approach is preferred. Alternatively, we could directly use the user-annotated value. - Both waves per eu and flat workgroup size exist: If there’s a conflict, the value derived from the flat workgroup size takes precedence over waves per eu. This PR also updates the logic for merging two waves per eu pairs. The current implementation, which uses `clampStateAndIndicateChange` to compute a union, might not be ideal. If we think from ensure proper resource allocation perspective, for instance, if one pair specifies a minimum of 2 waves per eu, and another specifies a minimum of 4, we should guarantee that 4 waves per eu can be supported, as failing to do so could result in excessive resource allocation per wave. A similar principle applies to the upper bound. Thus, the PR uses the following approach for merging two pairs, `lo_a,up_a` and `lo_b,up_b`: `max(lo_a, lo_b), max(up_a, up_b)`. This ensures that resource allocation adheres to the stricter constraints from both inputs. Fix #123092.
68 lines
2.4 KiB
LLVM
68 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s
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%0 = type { ptr, ptr }
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define internal fastcc i1 @widget(ptr %arg) {
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; CHECK-LABEL: define {{[^@]+}}@widget
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; CHECK-SAME: (ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[TMP0:%.*]], ptr [[ARG]], i64 0, i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = call fastcc double @baz(ptr [[TMP1]])
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; CHECK-NEXT: ret i1 false
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;
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bb:
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%tmp = getelementptr inbounds %0, ptr %arg, i64 0, i32 1
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%tmp1 = load ptr, ptr %tmp, align 8
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%tmp2 = call fastcc double @baz(ptr %tmp1)
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ret i1 false
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}
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define internal fastcc double @baz(ptr %arg) {
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; CHECK-LABEL: define {{[^@]+}}@baz
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; CHECK-SAME: (ptr [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARG]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = tail call double [[TMP1]]()
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[TMP0:%.*]], ptr [[ARG]], i64 0, i32 1
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; CHECK-NEXT: br label [[BB5:%.*]]
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; CHECK: bb5:
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; CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP4]], align 8
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; CHECK-NEXT: [[TMP7:%.*]] = call fastcc i1 @widget(ptr [[TMP6]])
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; CHECK-NEXT: br label [[BB5]]
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;
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bb:
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%tmp1 = load ptr, ptr %arg, align 8
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%tmp2 = tail call double %tmp1()
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br label %bb3
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bb3: ; preds = %bb
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%tmp4 = getelementptr inbounds %0, ptr %arg, i64 0, i32 1
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br label %bb5
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bb5: ; preds = %bb5, %bb3
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%tmp6 = load ptr, ptr %tmp4, align 8
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%tmp7 = call fastcc i1 @widget(ptr %tmp6)
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br label %bb5
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}
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define amdgpu_kernel void @entry() {
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; CHECK-LABEL: define {{[^@]+}}@entry
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; CHECK-SAME: () #[[ATTR0]] {
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; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [[TMP0:%.*]], align 8, addrspace(5)
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; CHECK-NEXT: [[CAST:%.*]] = addrspacecast ptr addrspace(5) [[ALLOCA]] to ptr
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; CHECK-NEXT: [[ARST:%.*]] = call double @baz(ptr [[CAST]])
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; CHECK-NEXT: ret void
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;
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%alloca = alloca %0, align 8, addrspace(5)
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%cast = addrspacecast ptr addrspace(5) %alloca to ptr
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%arst = call double @baz(ptr %cast)
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ret void
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}
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;.
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; CHECK: attributes #[[ATTR0]] = { "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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;.
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