9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
39 lines
1.1 KiB
LLVM
39 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
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; CHECK: {{^}}fcmp_sext:
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; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define amdgpu_kernel void @fcmp_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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entry:
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%0 = load float, ptr addrspace(1) %in
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%arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %in, i32 1
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%1 = load float, ptr addrspace(1) %arrayidx1
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%cmp = fcmp oeq float %0, %1
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%sext = sext i1 %cmp to i32
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store i32 %sext, ptr addrspace(1) %out
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ret void
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}
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; This test checks that a setcc node with f32 operands is lowered to a
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; SET*_DX10 instruction. Previously we were lowering this to:
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; SET* + FP_TO_SINT
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; CHECK: {{^}}fcmp_br:
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; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
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; CHECK-NEXT: {{[0-9]+\(5.0}}
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define amdgpu_kernel void @fcmp_br(ptr addrspace(1) %out, float %in) {
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entry:
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%0 = fcmp oeq float %in, 5.0
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br i1 %0, label %IF, label %ENDIF
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IF:
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%1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 0, ptr addrspace(1) %1
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br label %ENDIF
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ENDIF:
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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