fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
122 lines
3.8 KiB
LLVM
122 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.
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define amdgpu_hs void @wwm(i32 inreg %arg, ptr addrspace(8) inreg %buffer) {
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; GCN-LABEL: wwm:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_mov_b32 s6, s3
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; GCN-NEXT: s_mov_b32 s5, s2
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; GCN-NEXT: s_or_saveexec_b64 s[2:3], -1
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; GCN-NEXT: s_mov_b32 s7, s4
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; GCN-NEXT: s_mov_b32 s4, s1
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; GCN-NEXT: s_mov_b32 s1, 1
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; GCN-NEXT: v_cndmask_b32_e64 v0, 1, 4, s[2:3]
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-NEXT: s_mov_b64 exec, s[2:3]
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: v_mov_b32_e32 v1, v0
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; GCN-NEXT: s_cbranch_scc0 .LBB0_2
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; GCN-NEXT: ; %bb.1: ; %bb42
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; GCN-NEXT: s_mov_b32 s1, 0
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; GCN-NEXT: .LBB0_2: ; %bb602
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1
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; GCN-NEXT: s_cbranch_vccnz .LBB0_4
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; GCN-NEXT: ; %bb.3: ; %bb49
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; GCN-NEXT: v_mov_b32_e32 v1, 1.0
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; GCN-NEXT: tbuffer_store_format_x v1, off, s[4:7], 1 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] offset:4 glc
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; GCN-NEXT: .LBB0_4: ; %bb54
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; GCN-NEXT: s_endpgm
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entry:
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br label %work
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bb42:
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br label %bb602
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bb602:
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%tmp603 = phi i32 [ 0, %bb42 ], [ 1, %work ]
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%tmp607 = icmp eq i32 %tmp603, %tmp1196
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br i1 %tmp607, label %bb49, label %bb54
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bb49:
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call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float 1.0, ptr addrspace(8) %buffer, i32 4, i32 1, i32 116, i32 1)
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ret void
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bb54:
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ret void
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work:
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%tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)
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%tmp1191 = mul i32 %tmp1189, 4
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%tmp1196 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp1191)
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%tmp34 = icmp eq i32 %arg, 0
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br i1 %tmp34, label %bb602, label %bb42
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}
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define amdgpu_hs void @strict_wwm(i32 inreg %arg, ptr addrspace(8) inreg %buffer) {
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; GCN-LABEL: strict_wwm:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_mov_b32 s6, s3
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; GCN-NEXT: s_mov_b32 s5, s2
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; GCN-NEXT: s_or_saveexec_b64 s[2:3], -1
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; GCN-NEXT: s_mov_b32 s7, s4
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; GCN-NEXT: s_mov_b32 s4, s1
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; GCN-NEXT: s_mov_b32 s1, 1
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; GCN-NEXT: v_cndmask_b32_e64 v0, 1, 4, s[2:3]
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-NEXT: s_mov_b64 exec, s[2:3]
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: v_mov_b32_e32 v1, v0
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; GCN-NEXT: s_cbranch_scc0 .LBB1_2
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; GCN-NEXT: ; %bb.1: ; %bb42
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; GCN-NEXT: s_mov_b32 s1, 0
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; GCN-NEXT: .LBB1_2: ; %bb602
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1
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; GCN-NEXT: s_cbranch_vccnz .LBB1_4
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; GCN-NEXT: ; %bb.3: ; %bb49
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; GCN-NEXT: v_mov_b32_e32 v1, 1.0
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; GCN-NEXT: tbuffer_store_format_x v1, off, s[4:7], 1 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] offset:4 glc
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; GCN-NEXT: .LBB1_4: ; %bb54
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; GCN-NEXT: s_endpgm
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entry:
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br label %work
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bb42:
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br label %bb602
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bb602:
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%tmp603 = phi i32 [ 0, %bb42 ], [ 1, %work ]
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%tmp607 = icmp eq i32 %tmp603, %tmp1196
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br i1 %tmp607, label %bb49, label %bb54
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bb49:
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call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float 1.0, ptr addrspace(8) %buffer, i32 4, i32 1, i32 116, i32 1)
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ret void
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bb54:
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ret void
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work:
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%tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)
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%tmp1191 = mul i32 %tmp1189, 4
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%tmp1196 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp1191)
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%tmp34 = icmp eq i32 %arg, 0
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br i1 %tmp34, label %bb602, label %bb42
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0
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declare i32 @llvm.amdgcn.wwm.i32(i32) #1
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declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1
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declare void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float, ptr addrspace(8), i32, i32, i32 immarg, i32 immarg) #2
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attributes #0 = { convergent nounwind readnone willreturn }
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attributes #1 = { convergent nounwind readnone speculatable willreturn }
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attributes #2 = { nounwind willreturn memory(argmem: write) }
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