7c24041895
Previous patch is merged https://github.com/llvm/llvm-project/pull/114500 and it hit a buildbot failure and thus reverted It seems the AMDGPU::OpName::OPERAND_LAST is removed at the meantime when previous patch is merged and that's causing the compile error. Fixed and reopen it here
262 lines
10 KiB
LLVM
262 lines
10 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,CIVI %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,CIVI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,CIVI,CIVI-HSA %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10PLUS %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX11-FAKE16 %s
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; GCN-LABEL: {{^}}store_flat_i32:
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; GCN-DAG: s_load_{{dwordx2|b64}} s[[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]],
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; GCN-DAG: s_load_{{dword|b32}} s[[SDATA:[0-9]+]],
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]]
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; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
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; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
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; GCN: flat_store_{{dword|b32}} v[[[LO_VREG]]:[[HI_VREG]]], v[[DATA]]
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define amdgpu_kernel void @store_flat_i32(ptr addrspace(1) %gptr, i32 %x) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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store volatile i32 %x, ptr %fptr, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_i64:
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; GCN: flat_store_{{dword|b64}}
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define amdgpu_kernel void @store_flat_i64(ptr addrspace(1) %gptr, i64 %x) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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store volatile i64 %x, ptr %fptr, align 8
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_v4i32:
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; GCN: flat_store_{{dword|b128}}
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define amdgpu_kernel void @store_flat_v4i32(ptr addrspace(1) %gptr, <4 x i32> %x) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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store volatile <4 x i32> %x, ptr %fptr, align 16
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_trunc_i16:
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; GCN: flat_store_{{short|b16}}
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define amdgpu_kernel void @store_flat_trunc_i16(ptr addrspace(1) %gptr, i32 %x) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%y = trunc i32 %x to i16
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store volatile i16 %y, ptr %fptr, align 2
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_trunc_i8:
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; GCN: flat_store_{{byte|b8}}
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define amdgpu_kernel void @store_flat_trunc_i8(ptr addrspace(1) %gptr, i32 %x) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%y = trunc i32 %x to i8
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store volatile i8 %y, ptr %fptr, align 2
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ret void
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}
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; GCN-LABEL: load_flat_i32:
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; GCN: flat_load_{{dword|b32}}
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define amdgpu_kernel void @load_flat_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile i32, ptr %fptr, align 4
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store i32 %fload, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: load_flat_i64:
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; GCN: flat_load_{{dword|b64}}
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define amdgpu_kernel void @load_flat_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile i64, ptr %fptr, align 8
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store i64 %fload, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: load_flat_v4i32:
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; GCN: flat_load_{{dword|b128}}
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define amdgpu_kernel void @load_flat_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile <4 x i32>, ptr %fptr, align 32
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store <4 x i32> %fload, ptr addrspace(1) %out, align 8
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ret void
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}
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; GCN-LABEL: sextload_flat_i8:
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; GCN: flat_load_{{sbyte|i8}}
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define amdgpu_kernel void @sextload_flat_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile i8, ptr %fptr, align 4
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%ext = sext i8 %fload to i32
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store i32 %ext, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: zextload_flat_i8:
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; GCN: flat_load_{{ubyte|u8}}
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define amdgpu_kernel void @zextload_flat_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile i8, ptr %fptr, align 4
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%ext = zext i8 %fload to i32
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store i32 %ext, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: sextload_flat_i16:
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; GCN: flat_load_{{sshort|i16}}
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define amdgpu_kernel void @sextload_flat_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile i16, ptr %fptr, align 4
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%ext = sext i16 %fload to i32
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store i32 %ext, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: zextload_flat_i16:
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; GCN: flat_load_{{ushort|u16}}
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define amdgpu_kernel void @zextload_flat_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {
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%fptr = addrspacecast ptr addrspace(1) %gptr to ptr
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%fload = load volatile i16, ptr %fptr, align 4
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%ext = zext i16 %fload to i32
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store i32 %ext, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: flat_scratch_unaligned_load:
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; GFX9: flat_load_dword
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; GFX10PLUS: flat_load_{{dword|b32}}
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define amdgpu_kernel void @flat_scratch_unaligned_load() {
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%scratch = alloca i32, addrspace(5)
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%fptr = addrspacecast ptr addrspace(5) %scratch to ptr
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store volatile ptr %fptr, ptr addrspace(3) null
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%ld = load volatile i32, ptr %fptr, align 1
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ret void
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}
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; GCN-LABEL: flat_scratch_unaligned_store:
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; GFX9: flat_store_dword
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; GFX10PLUS: flat_store_{{dword|b32}}
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define amdgpu_kernel void @flat_scratch_unaligned_store() {
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%scratch = alloca i32, addrspace(5)
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%fptr = addrspacecast ptr addrspace(5) %scratch to ptr
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store volatile ptr %fptr, ptr addrspace(3) null
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store volatile i32 0, ptr %fptr, align 1
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ret void
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}
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; GCN-LABEL: flat_scratch_multidword_load_kernel:
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; CIVI-HSA: flat_load_dword v
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; CIVI-HSA: flat_load_dword v
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; GFX9: flat_load_dwordx2
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; GFX10PLUS: flat_load_{{dwordx2|b64}}
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; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
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define amdgpu_kernel void @flat_scratch_multidword_load_kernel() {
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%scratch = alloca <2 x i32>, addrspace(5)
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%fptr = addrspacecast ptr addrspace(5) %scratch to ptr
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%ld = load volatile <2 x i32>, ptr %fptr
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ret void
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}
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;
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; GCN-LABEL: flat_scratch_multidword_load_func:
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; CIVI-HSA: flat_load_dword v
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; CIVI-HSA: flat_load_dword v
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; GFX9: flat_load_dwordx2
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; GFX10PLUS: flat_load_{{dwordx2|b64}}
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; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
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define <2 x i32> @flat_scratch_multidword_load_func(ptr %maybe.scratch) {
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%load = load <2 x i32>, ptr %maybe.scratch
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ret <2 x i32> %load
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}
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; GCN-LABEL: flat_scratch_multidword_store_kernel:
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; CIVI-HSA: flat_store_dword v
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; CIVI-HSA: flat_store_dword v
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; GFX9: flat_store_dwordx2
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; GFX10PLUS: flat_store_{{dwordx2|b64}}
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; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
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define amdgpu_kernel void @flat_scratch_multidword_store_kernel() {
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%scratch = alloca <2 x i32>, addrspace(5)
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%fptr = addrspacecast ptr addrspace(5) %scratch to ptr
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store volatile <2 x i32> zeroinitializer, ptr %fptr
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ret void
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}
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; GCN-LABEL: flat_scratch_multidword_store_func:
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; CIVI-HSA: flat_store_dword v
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; CIVI-HSA: flat_store_dword v
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; GFX9: flat_store_dwordx2
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; GFX10PLUS: flat_store_{{dwordx2|b64}}
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define void @flat_scratch_multidword_store_func(ptr %maybe.scratch) {
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store <2 x i32> zeroinitializer, ptr %maybe.scratch
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_i8_max_offset:
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; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}}
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define amdgpu_kernel void @store_flat_i8_max_offset(ptr %fptr, i8 %x) #0 {
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%fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4095
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store volatile i8 %x, ptr %fptr.offset
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_i8_max_offset_p1:
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; GCN: flat_store_{{byte|b8}} v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{( dlc)?}}{{$}}
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define amdgpu_kernel void @store_flat_i8_max_offset_p1(ptr %fptr, i8 %x) #0 {
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%fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4096
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store volatile i8 %x, ptr %fptr.offset
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ret void
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}
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; GCN-LABEL: {{^}}store_flat_i8_neg_offset:
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; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,
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; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @store_flat_i8_neg_offset(ptr %fptr, i8 %x) #0 {
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%fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 -2
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store volatile i8 %x, ptr %fptr.offset
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ret void
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}
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; GCN-LABEL: {{^}}load_flat_i8_max_offset:
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; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc{{$}}
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; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
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; GFX11-TRUE16: flat_load_d16_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc dlc{{$}}
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; GFX11-FAKE16: flat_load_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc dlc{{$}}
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define amdgpu_kernel void @load_flat_i8_max_offset(ptr %fptr) #0 {
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%fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4095
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%val = load volatile i8, ptr %fptr.offset
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ret void
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}
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; GCN-LABEL: {{^}}load_flat_i8_max_offset_p1:
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; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
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; GFX11-TRUE16: flat_load_d16_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
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; GFX11-FAKE16: flat_load_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
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define amdgpu_kernel void @load_flat_i8_max_offset_p1(ptr %fptr) #0 {
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%fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4096
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%val = load volatile i8, ptr %fptr.offset
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ret void
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}
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; GCN-LABEL: {{^}}load_flat_i8_neg_offset:
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; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,
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; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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define amdgpu_kernel void @load_flat_i8_neg_offset(ptr %fptr) #0 {
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%fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 -2
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%val = load volatile i8, ptr %fptr.offset
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind convergent }
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