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llvm-project/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll
Brox Chen c50ed05cad
[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211) 
recreate this patch from
https://github.com/llvm/llvm-project/pull/153894

It seems ISel sliently ignore the `i64 = zext i16` with a chained
`reg_sequence` pattern and thus this is causing a selection failure in
hip test. Recreate a new patch with an alternative pattern, and added a
ll test global-extload-gfx11plus.ll
2025-08-20 10:26:49 -04:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-REAL16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_kernel void @zextload_global_i8_to_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-REAL16-LABEL: zextload_global_i8_to_i16:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
; GFX11-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-REAL16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: zextload_global_i8_to_i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%a = load i8, ptr addrspace(1) %in
%ext = zext i8 %a to i16
store i16 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @sextload_global_i8_to_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-REAL16-LABEL: sextload_global_i8_to_i16:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_i8 v0, v1, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
; GFX11-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-REAL16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: sextload_global_i8_to_i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_i8 v1, v0, s[2:3]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%a = load i8, ptr addrspace(1) %in
%ext = sext i8 %a to i16
store i16 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @zextload_global_i8_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-REAL16-LABEL: zextload_global_i8_to_i64:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
; GFX11-REAL16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-REAL16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
; GFX11-REAL16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: zextload_global_i8_to_i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_u8 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%a = load i8, ptr addrspace(1) %in
%ext = zext i8 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @sextload_global_i8_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-REAL16-LABEL: sextload_global_i8_to_i64:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_i8 v0, v2, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
; GFX11-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-REAL16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX11-REAL16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-REAL16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: sextload_global_i8_to_i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_i8 v0, v2, s[2:3]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%a = load i8, ptr addrspace(1) %in
%ext = sext i8 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @zextload_global_i16_to_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-LABEL: zextload_global_i16_to_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_load_u16 v1, v0, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %in
%ext = zext i16 %a to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @sextload_global_i16_to_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-LABEL: sextload_global_i16_to_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_load_i16 v1, v0, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %in
%ext = sext i16 %a to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @zextload_global_i16_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-REAL16-LABEL: zextload_global_i16_to_i64:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
; GFX11-REAL16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-REAL16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
; GFX11-REAL16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: zextload_global_i16_to_i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_u16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %in
%ext = zext i16 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @sextload_global_i16_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
; GFX11-REAL16-LABEL: sextload_global_i16_to_i64:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
; GFX11-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-REAL16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX11-REAL16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-REAL16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: sextload_global_i16_to_i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_u16 v0, v2, s[2:3]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX11-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %in
%ext = sext i16 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
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