9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
394 lines
14 KiB
LLVM
394 lines
14 KiB
LLVM
; RUN: llc -mtriple=r600 -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; === 1 image arg, read_only ===================================================
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; FUNC-LABEL: {{^}}test_2d_rd_1_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_2d_rd_1_0(ptr addrspace(1) %in, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_rd_1_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_3d_rd_1_0(ptr addrspace(1) %in, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; === 1 image arg, write_only ==================================================
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; FUNC-LABEL: {{^}}test_2d_wr_1_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_2d_wr_1_0(ptr addrspace(1) %in, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_wr_1_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_3d_wr_1_0(ptr addrspace(1) %in, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; === 2 image args, read_only ==================================================
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; FUNC-LABEL: {{^}}test_2d_rd_2_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_2d_rd_2_0(ptr addrspace(1) %in1, ; read_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in1) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_2d_rd_2_1:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_2d_rd_2_1(ptr addrspace(1) %in1, ; read_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in2) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_rd_2_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_3d_rd_2_0(ptr addrspace(1) %in1, ; read_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in1) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_rd_2_1:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_3d_rd_2_1(ptr addrspace(1) %in1, ; read_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in2) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; === 2 image args, write_only =================================================
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; FUNC-LABEL: {{^}}test_2d_wr_2_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_2d_wr_2_0(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in1) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_2d_wr_2_1:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_2d_wr_2_1(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in2) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_wr_2_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 0(
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define amdgpu_kernel void @test_3d_wr_2_0(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in1) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_wr_2_1:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_3d_wr_2_1(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in2) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; === 3 image args, read_only ==================================================
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; FUNC-LABEL: {{^}}test_2d_rd_3_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 2(
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define amdgpu_kernel void @test_2d_rd_3_0(ptr addrspace(1) %in1, ; read_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %in3, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_rd_3_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 2(
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define amdgpu_kernel void @test_3d_rd_3_0(ptr addrspace(1) %in1, ; read_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %in3, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; === 3 image args, write_only =================================================
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; FUNC-LABEL: {{^}}test_2d_wr_3_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 2(
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define amdgpu_kernel void @test_2d_wr_3_0(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; write_only
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ptr addrspace(1) %in3, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_wr_3_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 2(
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define amdgpu_kernel void @test_3d_wr_3_0(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; write_only
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ptr addrspace(1) %in3, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; === 3 image args, mixed ======================================================
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; FUNC-LABEL: {{^}}test_2d_mix_3_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_2d_mix_3_0(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %in3, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_mix_3_0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_3d_mix_3_0(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %in3, ; read_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_2d_mix_3_1:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_2d_mix_3_1(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %in3, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.2d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_3d_mix_3_1:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV [[VAL]], literal.x
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; EG-NEXT: LSHR
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; EG-NEXT: 1(
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define amdgpu_kernel void @test_3d_mix_3_1(ptr addrspace(1) %in1, ; write_only
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ptr addrspace(1) %in2, ; read_only
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ptr addrspace(1) %in3, ; write_only
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ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.OpenCL.image.get.resource.id.3d(
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ptr addrspace(1) %in3) #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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%opencl.image2d_t = type opaque
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%opencl.image3d_t = type opaque
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declare i32 @llvm.OpenCL.image.get.resource.id.2d(ptr addrspace(1)) #0
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declare i32 @llvm.OpenCL.image.get.resource.id.3d(ptr addrspace(1)) #0
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attributes #0 = { readnone }
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!opencl.kernels = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13,
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!14, !15, !16, !17, !18, !19}
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!0 = !{ptr @test_2d_rd_1_0,
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!110, !120, !130, !140, !150}
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!1 = !{ptr @test_3d_rd_1_0,
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!110, !120, !131, !141, !150}
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!2 = !{ptr @test_2d_wr_1_0,
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!110, !121, !130, !140, !150}
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!3 = !{ptr @test_3d_wr_1_0,
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!110, !121, !131, !141, !150}
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!110 = !{!"kernel_arg_addr_space", i32 1, i32 1}
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!120 = !{!"kernel_arg_access_qual", !"read_only", !"none"}
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!121 = !{!"kernel_arg_access_qual", !"write_only", !"none"}
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!130 = !{!"kernel_arg_type", !"image2d_t", !"int*"}
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!131 = !{!"kernel_arg_type", !"image3d_t", !"int*"}
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!140 = !{!"kernel_arg_base_type", !"image2d_t", !"int*"}
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!141 = !{!"kernel_arg_base_type", !"image3d_t", !"int*"}
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!150 = !{!"kernel_arg_type_qual", !"", !""}
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!4 = !{ptr @test_2d_rd_2_0, !112, !122, !132, !142, !152}
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!5 = !{ptr @test_2d_rd_2_1, !112, !122, !132, !142, !152}
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!6 = !{ptr @test_3d_rd_2_0, !112, !122, !133, !143, !152}
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!7 = !{ptr @test_3d_rd_2_1, !112, !122, !133, !143, !152}
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!8 = !{ptr @test_2d_wr_2_0, !112, !123, !132, !142, !152}
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!9 = !{ptr @test_2d_wr_2_1, !112, !123, !132, !142, !152}
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!10 = !{ptr @test_3d_wr_2_0, !112, !123, !133, !143, !152}
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!11 = !{ptr @test_3d_wr_2_1, !112, !123, !133, !143, !152}
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!112 = !{!"kernel_arg_addr_space", i32 1, i32 1, i32 1}
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!122 = !{!"kernel_arg_access_qual", !"read_only", !"read_only", !"none"}
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!123 = !{!"kernel_arg_access_qual", !"write_only", !"write_only", !"none"}
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!132 = !{!"kernel_arg_type", !"image2d_t", !"image2d_t", !"int*"}
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!133 = !{!"kernel_arg_type", !"image3d_t", !"image3d_t", !"int*"}
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!142 = !{!"kernel_arg_base_type", !"image2d_t", !"image2d_t", !"int*"}
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!143 = !{!"kernel_arg_base_type", !"image3d_t", !"image3d_t", !"int*"}
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!152 = !{!"kernel_arg_type_qual", !"", !"", !""}
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!12 = !{ptr @test_2d_rd_3_0,
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!114, !124, !134, !144, !154}
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!13 = !{ptr @test_3d_rd_3_0,
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!114, !124, !135, !145, !154}
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!14 = !{ptr @test_2d_wr_3_0,
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!114, !125, !134, !144, !154}
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!15 = !{ptr @test_3d_wr_3_0,
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!114, !125, !135, !145, !154}
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!16 = !{ptr @test_2d_mix_3_0,
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!114, !126, !134, !144, !154}
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!17 = !{ptr @test_3d_mix_3_0,
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|
!114, !126, !135, !145, !154}
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!18 = !{ptr @test_2d_mix_3_1,
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!114, !127, !134, !144, !154}
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!19 = !{ptr @test_3d_mix_3_1,
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!114, !127, !135, !145, !154}
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!114 = !{!"kernel_arg_addr_space", i32 1, i32 1, i32 1, i32 1}
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|
!124 = !{!"kernel_arg_access_qual", !"read_only", !"read_only", !"read_only", !"none"}
|
|
!125 = !{!"kernel_arg_access_qual", !"write_only", !"write_only", !"write_only", !"none"}
|
|
!126 = !{!"kernel_arg_access_qual", !"write_only", !"read_only", !"read_only", !"none"}
|
|
!127 = !{!"kernel_arg_access_qual", !"write_only", !"read_only", !"write_only", !"none"}
|
|
!134 = !{!"kernel_arg_type", !"image2d_t", !"image3d_t", !"image2d_t", !"int*"}
|
|
!135 = !{!"kernel_arg_type", !"image3d_t", !"image2d_t", !"image3d_t", !"int*"}
|
|
!144 = !{!"kernel_arg_base_type", !"image2d_t", !"image3d_t", !"image2d_t", !"int*"}
|
|
!145 = !{!"kernel_arg_base_type", !"image3d_t", !"image2d_t", !"image3d_t", !"int*"}
|
|
!154 = !{!"kernel_arg_type_qual", !"", !"", !"", !""}
|