shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
Chris Jackson 9f102a9004
[AMDGPU] Recognise bitmask operations as srcmods on select (#152119) 
Add to the VOP patterns to recognise when or/xor/and are masking only the most significant bit of i32/v2i32/i64 and replace with the corresponding FP source modifier.
2025-08-07 19:45:09 +01:00

1012 lines
38 KiB
LLVM
Raw Permalink Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define i32 @fneg_select_i32_1(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fneg_select_i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i32 %a, u0x80000000
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %b
ret i32 %select
}
define i32 @fneg_select_i32_2(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fneg_select_i32_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, -v1, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i32_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, -v1, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i32 %a, u0x80000000
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %b, i32 %neg.a
ret i32 %select
}
define i32 @fneg_select_i32_both(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fneg_select_i32_both:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i32_both:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i32 %a, u0x80000000
%neg.b = xor i32 %b, u0x80000000
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %neg.b
ret i32 %select
}
define i32 @fneg_1_fabs_2_select_i32(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fneg_1_fabs_2_select_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, |v1|, -v1, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_1_fabs_2_select_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, -v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i32 %a, u0x80000000
%abs.b = and i32 %a, u0x7fffffff
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %abs.b
ret i32 %select
}
define i32 @s_fneg_select_i32_1(i32 inreg %cond, i32 inreg %a, i32 inreg %b) {
; GCN-LABEL: s_fneg_select_i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_xor_b32 s4, s17, 0x80000000
; GCN-NEXT: s_cmp_eq_u32 s16, 0
; GCN-NEXT: s_cselect_b32 s4, s4, s18
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_select_i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_b32 s1, s1, 0x80000000
; GFX11-NEXT: s_cmp_eq_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i32 %a, u0x80000000
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %b
ret i32 %select
}
define i32 @s_fneg_1_fabs_2_select_i32(i32 inreg %cond, i32 %a, i32 %b) {
; GCN-LABEL: s_fneg_1_fabs_2_select_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_cmp_eq_u32 s16, 0
; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
; GCN-NEXT: v_cndmask_b32_e64 v0, |v0|, -v0, s[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_1_fabs_2_select_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_cmp_eq_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, |v0|, -v0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i32 %a, u0x80000000
%abs.b = and i32 %a, u0x7fffffff
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %abs.b
ret i32 %select
}
define <2 x i32> @fneg_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
; GCN-LABEL: fneg_select_v2i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_v2i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
ret <2 x i32> %select
}
define <2 x i32> @fneg_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
; GCN-LABEL: fneg_select_v2i32_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_v2i32_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, v4, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a
ret <2 x i32> %select
}
define i32 @fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fabs_select_i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fabs_select_i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i32 %a, u0x7fffffff
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %b
ret i32 %select
}
define i32 @fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fabs_select_i32_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fabs_select_i32_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i32 %a, u0x7fffffff
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %b, i32 %neg.a
ret i32 %select
}
define <2 x i32> @fneg_1_fabs_2_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
; GCN-LABEL: fneg_1_fabs_2_select_v2i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, |v2|, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, |v3|, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_1_fabs_2_select_v2i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, |v2|, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, |v3|, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
%abs.b = and <2 x i32> %a, splat (i32 u0x7fffffff)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %abs.b, <2 x i32> %neg.a
ret <2 x i32> %select
}
define i32 @fneg_fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fneg_fabs_select_i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -|v1|, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -|v1|, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i32 %a, u0x80000000
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %neg.a, i32 %b
ret i32 %select
}
define i32 @fneg_fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) {
; GCN-LABEL: fneg_fabs_select_i32_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, -|v1|, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_i32_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, -|v1|, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i32 %a, u0x80000000
%cmp = icmp eq i32 %cond, zeroinitializer
%select = select i1 %cmp, i32 %b, i32 %neg.a
ret i32 %select
}
define <2 x i32> @fneg_fabs_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
; GCN-LABEL: fneg_fabs_select_v2i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v4, -|v2|, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_v2i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -|v2|, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or <2 x i32> %a, splat (i32 u0x80000000)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
ret <2 x i32> %select
}
define <2 x i32> @fneg_fabs_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
; GCN-LABEL: fneg_fabs_select_v2i32_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, -|v2|, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_v2i32_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, -|v2|, v4, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or <2 x i32> %a, splat (i32 u0x80000000)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a
ret <2 x i32> %select
}
define <2 x i32> @s_fneg_select_v2i32_1(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) {
; GCN-LABEL: s_fneg_select_v2i32_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_xor_b32 s4, s19, 0x80000000
; GCN-NEXT: s_xor_b32 s5, s18, 0x80000000
; GCN-NEXT: s_cmp_eq_u32 s16, 0
; GCN-NEXT: s_cselect_b32 s5, s5, s20
; GCN-NEXT: s_cmp_eq_u32 s17, 0
; GCN-NEXT: s_cselect_b32 s4, s4, s21
; GCN-NEXT: v_mov_b32_e32 v0, s5
; GCN-NEXT: v_mov_b32_e32 v1, s4
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_select_v2i32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000
; GFX11-NEXT: s_xor_b32 s2, s2, 0x80000000
; GFX11-NEXT: s_cmp_eq_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s16
; GFX11-NEXT: s_cmp_eq_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, s3, s17
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
ret <2 x i32> %select
}
define <2 x i32> @s_fneg_fabs_select_v2i32_2(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) {
; GCN-LABEL: s_fneg_fabs_select_v2i32_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_bitset1_b32 s19, 31
; GCN-NEXT: s_bitset1_b32 s18, 31
; GCN-NEXT: s_cmp_eq_u32 s16, 0
; GCN-NEXT: s_cselect_b32 s4, s20, s18
; GCN-NEXT: s_cmp_eq_u32 s17, 0
; GCN-NEXT: s_cselect_b32 s5, s21, s19
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_fabs_select_v2i32_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_bitset1_b32 s3, 31
; GFX11-NEXT: s_bitset1_b32 s2, 31
; GFX11-NEXT: s_cmp_eq_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, s16, s2
; GFX11-NEXT: s_cmp_eq_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, s17, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or <2 x i32> %a, splat (i32 u0x80000000)
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
%select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a
ret <2 x i32> %select
}
define i64 @fneg_select_i64_1(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fneg_select_i64_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %b
ret i64 %select
}
define i64 @fneg_select_i64_2(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fneg_select_i64_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %b, i64 %neg.a
ret i64 %select
}
define i64 @fneg_1_fabs_2_select_i64(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fneg_1_fabs_2_select_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_1_fabs_2_select_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%abs.b = and i64 %b, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %abs.b
ret i64 %select
}
define i64 @fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fabs_select_i64_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fabs_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i64 %a, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %b
ret i64 %select
}
define i64 @fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fabs_select_i64_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fabs_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i64 %a, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %b, i64 %neg.a
ret i64 %select
}
define i64 @fneg_fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fneg_fabs_select_i64_1:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %b
ret i64 %select
}
define i64 @fneg_fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) {
; GCN-LABEL: fneg_fabs_select_i64_2:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: fneg_fabs_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %b, i64 %neg.a
ret i64 %select
}
define i64 @s_fneg_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fneg_select_i64_1:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s18, s20
; GFX7-NEXT: s_cselect_b32 s5, s6, s21
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fneg_select_i64_1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s5, s18, s20
; GFX9-NEXT: s_cselect_b32 s4, s4, s21
; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s16
; GFX11-NEXT: s_cselect_b32 s1, s3, s17
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %b
ret i64 %select
}
define i64 @s_fneg_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fneg_select_i64_2:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s20, s18
; GFX7-NEXT: s_cselect_b32 s5, s21, s6
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fneg_select_i64_2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s5, s20, s18
; GFX9-NEXT: s_cselect_b32 s4, s21, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s16, s2
; GFX11-NEXT: s_cselect_b32 s1, s17, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %b, i64 %neg.a
ret i64 %select
}
define i64 @s_fneg_1_fabs_2_select_i64(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fneg_1_fabs_2_select_i64:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000
; GFX7-NEXT: s_bitset0_b32 s21, 31
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s18, s20
; GFX7-NEXT: s_cselect_b32 s5, s6, s21
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fneg_1_fabs_2_select_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000
; GFX9-NEXT: s_bitset0_b32 s21, 31
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s5, s18, s20
; GFX9-NEXT: s_cselect_b32 s4, s4, s21
; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_1_fabs_2_select_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000
; GFX11-NEXT: s_bitset0_b32 s17, 31
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s16
; GFX11-NEXT: s_cselect_b32 s1, s3, s17
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i64 %a, u0x8000000000000000
%abs.b = and i64 %b, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %abs.b
ret i64 %select
}
define i64 @s_fabs_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fabs_select_i64_1:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_bitset0_b32 s19, 31
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s18, s20
; GFX7-NEXT: s_cselect_b32 s5, s19, s21
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fabs_select_i64_1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_bitset0_b32 s19, 31
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s4, s18, s20
; GFX9-NEXT: s_cselect_b32 s5, s19, s21
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fabs_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_bitset0_b32 s3, 31
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s16
; GFX11-NEXT: s_cselect_b32 s1, s3, s17
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i64 %a, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %b
ret i64 %select
}
define i64 @s_fabs_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fabs_select_i64_2:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_bitset0_b32 s19, 31
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s20, s18
; GFX7-NEXT: s_cselect_b32 s5, s21, s19
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fabs_select_i64_2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_bitset0_b32 s19, 31
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s4, s20, s18
; GFX9-NEXT: s_cselect_b32 s5, s21, s19
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fabs_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_bitset0_b32 s3, 31
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s16, s2
; GFX11-NEXT: s_cselect_b32 s1, s17, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = and i64 %a, u0x7fffffffffffffff
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %b, i64 %neg.a
ret i64 %select
}
define i64 @s_fneg_fabs_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fneg_fabs_select_i64_1:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_bitset1_b32 s19, 31
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s18, s20
; GFX7-NEXT: s_cselect_b32 s5, s19, s21
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fneg_fabs_select_i64_1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_bitset1_b32 s19, 31
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s4, s18, s20
; GFX9-NEXT: s_cselect_b32 s5, s19, s21
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_fabs_select_i64_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_bitset1_b32 s3, 31
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s16
; GFX11-NEXT: s_cselect_b32 s1, s3, s17
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %neg.a, i64 %b
ret i64 %select
}
define i64 @s_fneg_fabs_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_fneg_fabs_select_i64_2:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0
; GFX7-NEXT: s_bitset1_b32 s19, 31
; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX7-NEXT: s_cselect_b32 s4, s20, s18
; GFX7-NEXT: s_cselect_b32 s5, s21, s19
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_fneg_fabs_select_i64_2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_bitset1_b32 s19, 31
; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0
; GFX9-NEXT: s_cselect_b32 s4, s20, s18
; GFX9-NEXT: s_cselect_b32 s5, s21, s19
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_fneg_fabs_select_i64_2:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_bitset1_b32 s3, 31
; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0
; GFX11-NEXT: s_cselect_b32 s0, s16, s2
; GFX11-NEXT: s_cselect_b32 s1, s17, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.a = or i64 %a, u0x8000000000000000
%cmp = icmp eq i64 %cond, zeroinitializer
%select = select i1 %cmp, i64 %b, i64 %neg.a
ret i64 %select
}
define i16 @fneg_select_i16_1(i16 %cond, i16 %a, i16 %b) {
; GFX7-LABEL: fneg_select_i16_1:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fneg_select_i16_1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fneg_select_i16_1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fneg_select_i16_1:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i16 %a, u0x8000
%cmp = icmp eq i16 %cond, zeroinitializer
%select = select i1 %cmp, i16 %neg.a, i16 %b
ret i16 %select
}
define i16 @fneg_select_i16_2(i16 %cond, i16 %a, i16 %b) {
; GFX7-LABEL: fneg_select_i16_2:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fneg_select_i16_2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fneg_select_i16_2:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v2.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fneg_select_i16_2:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i16 %a, u0x8000
%cmp = icmp eq i16 %cond, zeroinitializer
%select = select i1 %cmp, i16 %b, i16 %neg.a
ret i16 %select
}
define i16 @fneg_select_i16_both(i16 %cond, i16 %a, i16 %b) {
; GFX7-LABEL: fneg_select_i16_both:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX7-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fneg_select_i16_both:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fneg_select_i16_both:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fneg_select_i16_both:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i16 %a, u0x8000
%neg.b = xor i16 %b, u0x8000
%cmp = icmp eq i16 %cond, zeroinitializer
%select = select i1 %cmp, i16 %neg.a, i16 %neg.b
ret i16 %select
}
define i16 @fneg_1_fabs_2_select_i16(i16 %cond, i16 %a, i16 %b) {
; GFX7-LABEL: fneg_1_fabs_2_select_i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1
; GFX7-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fneg_1_fabs_2_select_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: fneg_1_fabs_2_select_i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fneg_1_fabs_2_select_i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%neg.a = xor i16 %a, u0x8000
%abs.b = and i16 %a, u0x7fff
%cmp = icmp eq i16 %cond, zeroinitializer
%select = select i1 %cmp, i16 %neg.a, i16 %abs.b
ret i16 %select
}
Reference in New Issue View Git Blame Copy Permalink