9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
70 lines
2.4 KiB
LLVM
70 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; Check we can compile this test without infinite loop in the
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; DAG.computeKnownBits() due to missing (Depth + 1) argument in
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; call to it from computeKnownBitsForTargetNode().
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; Check that we actually have that target 24 bit multiplication
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; node produced.
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; GCN: v_mul_u32_u24
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define amdgpu_kernel void @test(ptr addrspace(1) nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb4
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bb1: ; preds = %bb4
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%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %tmp46
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store i32 %tmp46, ptr addrspace(1) %tmp3, align 4
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ret void
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bb4: ; preds = %bb4, %bb
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%tmp5 = phi i32 [ 0, %bb ], [ %tmp87, %bb4 ]
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%tmp6 = phi i32 [ %tmp, %bb ], [ %tmp46, %bb4 ]
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%tmp7 = ashr i32 %tmp6, 16
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%tmp8 = mul nsw i32 %tmp7, %tmp7
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%tmp9 = lshr i32 %tmp8, 16
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%tmp10 = mul nuw nsw i32 %tmp9, %tmp9
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%tmp11 = lshr i32 %tmp10, 16
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%tmp12 = mul nuw nsw i32 %tmp11, %tmp11
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%tmp13 = lshr i32 %tmp12, 16
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%tmp14 = mul nuw nsw i32 %tmp13, %tmp13
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%tmp15 = lshr i32 %tmp14, 16
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%tmp16 = mul nuw nsw i32 %tmp15, %tmp15
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%tmp17 = lshr i32 %tmp16, 16
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%tmp18 = mul nuw nsw i32 %tmp17, %tmp17
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%tmp19 = lshr i32 %tmp18, 16
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%tmp20 = mul nuw nsw i32 %tmp19, %tmp19
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%tmp21 = lshr i32 %tmp20, 16
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%tmp22 = mul nuw nsw i32 %tmp21, %tmp21
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%tmp23 = lshr i32 %tmp22, 16
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%tmp24 = mul nuw nsw i32 %tmp23, %tmp23
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%tmp25 = lshr i32 %tmp24, 16
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%tmp26 = mul nuw nsw i32 %tmp25, %tmp25
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%tmp27 = lshr i32 %tmp26, 16
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%tmp28 = mul nuw nsw i32 %tmp27, %tmp27
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%tmp29 = lshr i32 %tmp28, 16
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%tmp30 = mul nuw nsw i32 %tmp29, %tmp29
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%tmp31 = lshr i32 %tmp30, 16
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%tmp32 = mul nuw nsw i32 %tmp31, %tmp31
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%tmp33 = lshr i32 %tmp32, 16
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%tmp34 = mul nuw nsw i32 %tmp33, %tmp33
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%tmp35 = lshr i32 %tmp34, 16
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%tmp36 = mul nuw nsw i32 %tmp35, %tmp35
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%tmp37 = lshr i32 %tmp36, 16
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%tmp38 = mul nuw nsw i32 %tmp37, %tmp37
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%tmp39 = lshr i32 %tmp38, 16
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%tmp40 = mul nuw nsw i32 %tmp39, %tmp39
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%tmp41 = lshr i32 %tmp40, 16
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%tmp42 = mul nuw nsw i32 %tmp41, %tmp41
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%tmp43 = lshr i32 %tmp42, 16
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%tmp44 = mul nuw nsw i32 %tmp43, %tmp43
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%tmp45 = lshr i32 %tmp44, 16
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%tmp46 = mul nuw nsw i32 %tmp45, %tmp45
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%tmp87 = add nuw nsw i32 %tmp5, 1
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%tmp88 = icmp eq i32 %tmp87, 1000
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br i1 %tmp88, label %bb1, label %bb4
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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