fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
191 lines
4.5 KiB
LLVM
191 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-enable-ds128 < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-enable-ds128 < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
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; Testing for ds_read/write_b128
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
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; FUNC-LABEL: {{^}}local_load_i64:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}
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; GCN: ds_write_b64 v{{[0-9]+}}, [[VAL]]
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
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%ld = load i64, ptr addrspace(3) %in
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store i64 %ld, ptr addrspace(3) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v2i64:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v2i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
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entry:
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%ld = load <2 x i64>, ptr addrspace(3) %in
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store <2 x i64> %ld, ptr addrspace(3) %out
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ret void
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}
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; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
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; FUNC-LABEL: {{^}}local_load_v2i64_to_128:
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; CIVI: ds_read_b128
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; CIVI: ds_write_b128
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define amdgpu_kernel void @local_load_v2i64_to_128(ptr addrspace(3) %out, ptr addrspace(3) %in) {
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entry:
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%ld = load <2 x i64>, ptr addrspace(3) %in, align 16
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store <2 x i64> %ld, ptr addrspace(3) %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v3i64:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: ds_read2_b64
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; GCN-DAG: ds_read_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v3i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
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entry:
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%ld = load <3 x i64>, ptr addrspace(3) %in
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store <3 x i64> %ld, ptr addrspace(3) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v4i64:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v4i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
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entry:
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%ld = load <4 x i64>, ptr addrspace(3) %in
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store <4 x i64> %ld, ptr addrspace(3) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v8i64:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v8i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
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entry:
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%ld = load <8 x i64>, ptr addrspace(3) %in
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store <8 x i64> %ld, ptr addrspace(3) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v16i64:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v16i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
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entry:
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%ld = load <16 x i64>, ptr addrspace(3) %in
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store <16 x i64> %ld, ptr addrspace(3) %out
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ret void
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}
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attributes #0 = { nounwind }
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