9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
82 lines
2.2 KiB
LLVM
82 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test_a:
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; EG-NOT: CND
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; EG: SET{{[NEQGTL]+}}_DX10
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define amdgpu_kernel void @test_a(ptr addrspace(1) %out, float %in) {
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entry:
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%0 = fcmp olt float %in, 0.000000e+00
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fneg float %1
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%3 = fptosi float %2 to i32
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%4 = bitcast i32 %3 to float
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%5 = bitcast float %4 to i32
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%6 = icmp ne i32 %5, 0
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br i1 %6, label %IF, label %ENDIF
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IF:
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%7 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 0, ptr addrspace(1) %7
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br label %ENDIF
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ENDIF:
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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; Same as test_a, but the branch labels are swapped to produce the inverse cc
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; for the icmp instruction
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; EG-LABEL: {{^}}test_b:
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; EG: SET{{[GTEQN]+}}_DX10
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; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
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; EG-NEXT: PRED_
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; EG-NEXT: ALU clause starting
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define amdgpu_kernel void @test_b(ptr addrspace(1) %out, float %in) {
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entry:
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%0 = fcmp olt float %in, 0.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fneg float %1
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%3 = fptosi float %2 to i32
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%4 = bitcast i32 %3 to float
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%5 = bitcast float %4 to i32
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%6 = icmp ne i32 %5, 0
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br i1 %6, label %ENDIF, label %IF
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IF:
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%7 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 0, ptr addrspace(1) %7
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br label %ENDIF
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ENDIF:
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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; Test a CND*_INT instruction with float true/false values
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; EG-LABEL: {{^}}test_c:
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; EG: CND{{[GTE]+}}_INT
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define amdgpu_kernel void @test_c(ptr addrspace(1) %out, i32 %in) {
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entry:
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%0 = icmp sgt i32 %in, 0
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%1 = select i1 %0, float 2.0, float 3.0
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store float %1, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}selectcc_bool:
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; SI: s_cmp_lg_u32
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; SI: v_cndmask_b32_e64
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; SI-NOT: cmp
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; SI-NOT: cndmask
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define amdgpu_kernel void @selectcc_bool(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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%ext = select i1 %icmp0, i32 -1, i32 0
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store i32 %ext, ptr addrspace(1) %out
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ret void
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}
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