9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
30 lines
1011 B
LLVM
30 lines
1011 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck %s
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; SelectionDAG generates a setcc node with multiple uses:
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;
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; t21: i1 = setcc t3, Constant:i32<0>, setne:ch
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; t15: i32,i1 = subcarry Constant:i32<1>, Constant:i32<0>, t21
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; t23: i32 = select t21, t15, Constant:i32<0>
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define i32 @f() {
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; CHECK-LABEL: f:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_read_b32 v0, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = load i32, ptr addrspace(3) null, align 16
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%i6 = icmp ult i32 0, %i
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%i7 = sext i1 %i6 to i32
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%i8 = add i32 %i7, 1
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%i9 = and i32 %i8, %i7
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ret i32 %i9
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}
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