fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
52 lines
1.7 KiB
LLVM
52 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; Test that we correctly commute a sub instruction
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; FUNC-LABEL: {{^}}sub_rev:
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; SI-NOT: v_sub_i32_e32 v{{[0-9]+}}, vcc, s
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; SI: v_subrev_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, s
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; ModuleID = 'vop-shrink.ll'
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define amdgpu_kernel void @sub_rev(ptr addrspace(1) %out, <4 x i32> %sgpr, i32 %cond) {
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entry:
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%vgpr = call i32 @llvm.amdgcn.workitem.id.x() #1
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%tmp = icmp eq i32 %cond, 0
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br i1 %tmp, label %if, label %else
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if: ; preds = %entry
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%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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%tmp2 = extractelement <4 x i32> %sgpr, i32 1
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store i32 %tmp2, ptr addrspace(1) %out
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br label %endif
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else: ; preds = %entry
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%tmp3 = extractelement <4 x i32> %sgpr, i32 2
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%tmp4 = sub i32 %vgpr, %tmp3
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store i32 %tmp4, ptr addrspace(1) %out
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br label %endif
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endif: ; preds = %else, %if
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ret void
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}
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; Test that we fold an immediate that was illegal for a 64-bit op into the
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; 32-bit op when we shrink it.
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; FUNC-LABEL: {{^}}add_fold:
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; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000
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define amdgpu_kernel void @add_fold(ptr addrspace(1) %out) {
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entry:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = uitofp i32 %tmp to float
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%tmp2 = fadd float %tmp1, 1.024000e+03
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store float %tmp2, ptr addrspace(1) %out
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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