fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
97 lines
4.0 KiB
LLVM
97 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to
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; create vselects with i64 condition masks.
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; FIXME: Should be able to avoid intermediate vselect
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define amdgpu_kernel void @widen_vselect_and_mask_v4f64(<4 x double> %arg) #0 {
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; GCN-LABEL: widen_vselect_and_mask_v4f64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], 16
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: v_mov_b32_e32 v1, v0
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; GCN-NEXT: v_mov_b32_e32 v2, v0
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; GCN-NEXT: v_mov_b32_e32 v3, v0
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
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; GCN-NEXT: v_cmp_u_f64_e64 s[2:3], s[0:1], s[0:1]
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; GCN-NEXT: s_waitcnt expcnt(0)
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; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[2:3]
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; GCN-NEXT: v_cmp_neq_f64_e64 s[0:1], s[0:1], 0
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[1:2]
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; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
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; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
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; GCN-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
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; GCN-NEXT: s_mov_b64 s[4:5], 0
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; GCN-NEXT: v_mov_b32_e32 v2, v0
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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bb:
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%tmp = extractelement <4 x double> %arg, i64 0
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%tmp1 = fcmp uno double %tmp, 0.000000e+00
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%tmp2 = sext i1 %tmp1 to i64
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%tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 0
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%tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 1
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%tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 2
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%tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 3
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%tmp7 = fcmp une <4 x double> %arg, zeroinitializer
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%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
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%tmp9 = and <4 x i1> %tmp8, %tmp7
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%tmp10 = select <4 x i1> %tmp9, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, <4 x double> zeroinitializer
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store <4 x double> %tmp10, ptr addrspace(1) null, align 32
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ret void
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}
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define amdgpu_kernel void @widen_vselect_and_mask_v4i64(<4 x i64> %arg) #0 {
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; GCN-LABEL: widen_vselect_and_mask_v4i64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], 0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_mov_b64 s[8:9], 16
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; GCN-NEXT: s_mov_b32 s11, 0xf000
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; GCN-NEXT: s_mov_b32 s10, -1
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; GCN-NEXT: v_mov_b32_e32 v1, v0
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; GCN-NEXT: v_mov_b32_e32 v2, v0
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; GCN-NEXT: v_mov_b32_e32 v3, v0
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; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[0:1], 0
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; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[2:3]
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; GCN-NEXT: v_cmp_ne_u64_e64 s[0:1], s[0:1], 0
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; GCN-NEXT: v_mov_b32_e32 v5, v4
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; GCN-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[4:5]
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; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
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; GCN-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
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; GCN-NEXT: v_mov_b32_e32 v5, v0
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; GCN-NEXT: v_mov_b32_e32 v6, v0
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; GCN-NEXT: v_mov_b32_e32 v7, v0
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; GCN-NEXT: s_mov_b32 s6, s10
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; GCN-NEXT: s_mov_b32 s7, s11
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; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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bb:
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%tmp = extractelement <4 x i64> %arg, i64 0
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%tmp1 = icmp eq i64 %tmp, 0
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%tmp2 = sext i1 %tmp1 to i64
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%tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 0
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%tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 1
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%tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 2
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%tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 3
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%tmp7 = icmp ne <4 x i64> %arg, zeroinitializer
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%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
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%tmp9 = and <4 x i1> %tmp8, %tmp7
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%tmp10 = select <4 x i1> %tmp9, <4 x i64> <i64 1, i64 1, i64 1, i64 1>, <4 x i64> zeroinitializer
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store <4 x i64> %tmp10, ptr addrspace(1) null, align 32
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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