7852ebc088
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
67 lines
1.6 KiB
LLVM
67 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=bpfel -mcpu=v1 -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex --mcpu=v1 -d - | FileCheck %s
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; Source Code:
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; int gbl;
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; int test(int a, int b) {
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; if (a == 2) {
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; gbl = gbl * gbl * 2;
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; goto out;
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; }
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; if (a != b) {
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; gbl = gbl * 4;
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; }
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; out:
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; return gbl;
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; }
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@gbl = common local_unnamed_addr global i32 0, align 4
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define i32 @test(i32, i32) local_unnamed_addr #0 {
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%3 = icmp eq i32 %0, 2
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br i1 %3, label %4, label %8
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; <label>:4: ; preds = %2
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%5 = load i32, ptr @gbl, align 4
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%6 = shl i32 %5, 1
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%7 = mul i32 %6, %5
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br label %13
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; CHECK: r1 <<= 32
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; CHECK: r1 >>= 32
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; CHECK: if r1 != 2 goto +6 <test+0x48>
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; <label>:8: ; preds = %2
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%9 = icmp eq i32 %0, %1
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%10 = load i32, ptr @gbl, align 4
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br i1 %9, label %15, label %11
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; CHECK: r1 = 0 ll
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; CHECK: r0 = *(u32 *)(r1 + 0)
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; CHECK: r0 *= r0
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; CHECK: r0 <<= 1
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; CHECK: goto +7 <test+0x80>
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; <label>:11: ; preds = %8
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%12 = shl nsw i32 %10, 2
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br label %13
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; CHECK: r3 = 0 ll
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; CHECK: r0 = *(u32 *)(r3 + 0)
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; CHECK: r2 <<= 32
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; CHECK: r2 >>= 32
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; CHECK: if r1 == r2 goto +4 <test+0x98>
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; CHECK: r0 <<= 2
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; <label>:13: ; preds = %4, %11
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%14 = phi i32 [ %12, %11 ], [ %7, %4 ]
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store i32 %14, ptr @gbl, align 4
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br label %15
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; CHECK: r1 = 0 ll
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; CHECK: *(u32 *)(r1 + 0) = r0
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; <label>:15: ; preds = %8, %13
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%16 = phi i32 [ %14, %13 ], [ %10, %8 ]
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ret i32 %16
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; CHECK: exit
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}
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attributes #0 = { norecurse nounwind }
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