7852ebc088
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
66 lines
2.3 KiB
LLVM
66 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=bpfel -mcpu=v1 -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-DEC %s
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; RUN: llc -mtriple=bpfel -mcpu=v1 -filetype=obj -o - %s | llvm-objdump -d --print-imm-hex - | FileCheck --check-prefix=CHECK-HEX %s
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; Source Code:
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; int gbl;
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; int test(unsigned long long a, unsigned long long b) {
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; int ret = 0;
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; if (a == 0xABCDABCDabcdabcdULL) {
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; gbl = gbl * gbl * 2;
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; ret = 1;
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; goto out;
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; }
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; if (b == 0xABCDabcdabcdULL) {
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; gbl = gbl * 4;
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; ret = 2;
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; }
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; out:
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; return ret;
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; }
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@gbl = common local_unnamed_addr global i32 0, align 4
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; Function Attrs: norecurse nounwind
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define i32 @test(i64, i64) local_unnamed_addr #0 {
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; CHECK-LABEL: test
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%3 = icmp eq i64 %0, -6067004223159161907
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br i1 %3, label %4, label %8
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; CHECK-DEC: 18 03 00 00 cd ab cd ab 00 00 00 00 cd ab cd ab r3 = -6067004223159161907 ll
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; CHECK-DEC: 5d 31 07 00 00 00 00 00 if r1 != r3 goto +7
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; CHECK-HEX: 18 03 00 00 cd ab cd ab 00 00 00 00 cd ab cd ab r3 = -0x5432543254325433 ll
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; CHECK-HEX: 5d 31 07 00 00 00 00 00 if r1 != r3 goto +0x7
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; <label>:4: ; preds = %2
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%5 = load i32, ptr @gbl, align 4
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%6 = shl i32 %5, 1
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; CHECK-DEC: 67 01 00 00 01 00 00 00 r1 <<= 1
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; CHECK-HEX: 67 01 00 00 01 00 00 00 r1 <<= 0x1
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%7 = mul i32 %6, %5
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br label %13
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; <label>:8: ; preds = %2
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%9 = icmp eq i64 %1, 188899839028173
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; CHECK-DEC: 18 01 00 00 cd ab cd ab 00 00 00 00 cd ab 00 00 r1 = 188899839028173 ll
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; CHECK-HEX: 18 01 00 00 cd ab cd ab 00 00 00 00 cd ab 00 00 r1 = 0xabcdabcdabcd ll
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br i1 %9, label %10, label %16
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; <label>:10: ; preds = %8
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%11 = load i32, ptr @gbl, align 4
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%12 = shl nsw i32 %11, 2
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br label %13
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; <label>:13: ; preds = %4, %10
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%14 = phi i32 [ %12, %10 ], [ %7, %4 ]
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%15 = phi i32 [ 2, %10 ], [ 1, %4 ]
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store i32 %14, ptr @gbl, align 4
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; CHECK-DEC: 63 12 00 00 00 00 00 00 *(u32 *)(r2 + 0) = w1
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; CHECK-HEX: 63 12 00 00 00 00 00 00 *(u32 *)(r2 + 0x0) = w1
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br label %16
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; <label>:16: ; preds = %13, %8
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%17 = phi i32 [ 0, %8 ], [ %15, %13 ]
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ret i32 %17
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}
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attributes #0 = { norecurse nounwind }
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