5dbd8772fe
fixes #140321 Specifically it fixes ` error: Cannot create BufferLoad operation: Invalid overload type` https://hlsl.godbolt.org/z/dTq4q7o58 but no new DML shaders are building. This change now exposes #144747. The change does two things it adds i64 support for intrinsic expansion for the `dx_resource_load_typedbuffer`, and `dx_resource_store_typedbuffer` intrinsics. It also lets loaded typedbuffers crash more gracefully because of ` auto *EVI = cast<ExtractValueInst>(U);` is now a `dyn_cast` and `llvm_unreachable`.
49 lines
3.2 KiB
LLVM
49 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -dxil-intrinsic-expansion %s | FileCheck %s
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target triple = "dxil-pc-shadermodel6.2-compute"
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define void @loadi64() {
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; CHECK-LABEL: define void @loadi64() {
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; CHECK-NEXT: [[BUFFER:%.*]] = tail call target("dx.TypedBuffer", i64, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i64_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null)
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; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, i1 } @llvm.dx.resource.load.typedbuffer.v2i32.tdx.TypedBuffer_i64_1_0_0t(target("dx.TypedBuffer", i64, 1, 0, 0) [[BUFFER]], i32 0)
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; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, i1 } [[TMP1]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
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; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 32
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; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]
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; CHECK-NEXT: ret void
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;
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%buffer = tail call target("dx.TypedBuffer", i64, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i64_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null)
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%result = call { i64, i1 } @llvm.dx.resource.load.typedbuffer.tdx.TypedBuffer_i64_1_0_0t(target("dx.TypedBuffer", i64, 1, 0, 0) %buffer, i32 0)
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ret void
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}
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define void @loadv2i64() {
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; CHECK-LABEL: define void @loadv2i64() {
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; CHECK-NEXT: [[BUFFER:%.*]] = tail call target("dx.TypedBuffer", <2 x i64>, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v2i64_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null)
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; CHECK-NEXT: [[TMP1:%.*]] = call { <4 x i32>, i1 } @llvm.dx.resource.load.typedbuffer.v4i32.tdx.TypedBuffer_v2i64_1_0_0t(target("dx.TypedBuffer", <2 x i64>, 1, 0, 0) [[BUFFER]], i32 0)
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; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, i1 } [[TMP1]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
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; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP4]] to i64
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; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 32
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; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP7]], [[TMP9]]
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; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> poison, i64 [[TMP10]], i32 0
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; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: [[TMP14:%.*]] = shl i64 [[TMP13]], 32
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; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP12]], [[TMP14]]
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; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x i64> [[TMP11]], i64 [[TMP15]], i32 1
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; CHECK-NEXT: ret void
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;
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%buffer = tail call target("dx.TypedBuffer", <2 x i64>, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v2i64_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr null)
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%result = call { <2 x i64>, i1 } @llvm.dx.resource.load.typedbuffer.tdx.TypedBuffer_v2i64_1_0_0t(target("dx.TypedBuffer", <2 x i64>, 1, 0, 0) %buffer, i32 0)
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ret void
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}
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