2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
44 lines
2.0 KiB
LLVM
44 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=hexagon -disable-hsdr -enable-subreg-liveness < %s | FileCheck %s
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; Check that we don't generate any bitwise operations.
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; CHECK-NOT: = or(
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; CHECK-NOT: = and(
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target triple = "hexagon"
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define i32 @fred(ptr nocapture readonly %p, i32 %n) #0 {
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entry:
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%t.sroa.0.048 = load i32, ptr %p, align 4
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%cmp49 = icmp ugt i32 %n, 1
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br i1 %cmp49, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%t.sroa.0.052 = phi i32 [ %t.sroa.0.0, %for.body ], [ %t.sroa.0.048, %entry ]
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%t.sroa.11.051 = phi i64 [ %t.sroa.11.0.extract.shift, %for.body ], [ 0, %entry ]
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%i.050 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
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%t.sroa.0.0.insert.ext = zext i32 %t.sroa.0.052 to i64
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%t.sroa.0.0.insert.insert = or i64 %t.sroa.0.0.insert.ext, %t.sroa.11.051
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%0 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert, i64 %t.sroa.0.0.insert.insert)
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%t.sroa.11.0.extract.shift = and i64 %0, -4294967296
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%arrayidx4 = getelementptr inbounds i32, ptr %p, i32 %i.050
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%inc = add nuw i32 %i.050, 1
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%t.sroa.0.0 = load i32, ptr %arrayidx4, align 4
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%exitcond = icmp eq i32 %inc, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%t.sroa.0.0.lcssa = phi i32 [ %t.sroa.0.048, %entry ], [ %t.sroa.0.0, %for.body ]
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%t.sroa.11.0.lcssa = phi i64 [ 0, %entry ], [ %t.sroa.11.0.extract.shift, %for.body ]
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%t.sroa.0.0.insert.ext17 = zext i32 %t.sroa.0.0.lcssa to i64
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%t.sroa.0.0.insert.insert19 = or i64 %t.sroa.0.0.insert.ext17, %t.sroa.11.0.lcssa
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%1 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert19, i64 %t.sroa.0.0.insert.insert19)
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%t.sroa.11.0.extract.shift41 = lshr i64 %1, 32
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%t.sroa.11.0.extract.trunc42 = trunc i64 %t.sroa.11.0.extract.shift41 to i32
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ret i32 %t.sroa.11.0.extract.trunc42
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}
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declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
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attributes #0 = { norecurse nounwind readonly }
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attributes #1 = { nounwind readnone }
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