llvm-project/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll
Fangrui Song 2208c97c1b [Hexagon,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449

-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
2024-12-15 10:20:22 -08:00

25 lines
622 B
LLVM

; RUN: llc -mtriple=hexagon -hexbit-extract=0 < %s | FileCheck %s
; Make sure we don't generate zxtb to transfer a predicate register into
; a general purpose register.
; CHECK: r0 = p0
; CHECK-NOT: zxtb(p
; CHECK-NOT: and(p
; CHECK-NOT: extract(p
; CHECK-NOT: extractu(p
target triple = "hexagon"
; Function Attrs: nounwind
define i32 @fred() local_unnamed_addr #0 {
entry:
%0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef)
ret i32 %0
}
declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv5" }
attributes #1 = { nounwind readnone }