317 lines
8.3 KiB
LLVM
317 lines
8.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=hexagon -hexagon-bit=0 < %s | FileCheck %s
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; Optimized bitwise operations.
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define i32 @my_clrbit(i32 %x) nounwind {
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; CHECK-LABEL: my_clrbit:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = clrbit(r0,#31)
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; CHECK-NEXT: r1 = r0
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memw(r29+#4) = r1
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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%and = and i32 %0, 2147483647
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ret i32 %and
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}
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define i64 @my_clrbit2(i64 %x) nounwind {
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; CHECK-LABEL: my_clrbit2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = clrbit(r0,#31)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%and = and i64 %0, -2147483649
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ret i64 %and
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}
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define i64 @my_clrbit3(i64 %x) nounwind {
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; CHECK-LABEL: my_clrbit3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = clrbit(r1,#31)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%and = and i64 %0, 9223372036854775807
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ret i64 %and
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}
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define i32 @my_clrbit4(i32 %x) nounwind {
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; CHECK-LABEL: my_clrbit4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = clrbit(r0,#13)
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; CHECK-NEXT: r1 = r0
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memw(r29+#4) = r1
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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%and = and i32 %0, -8193
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ret i32 %and
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}
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define i64 @my_clrbit5(i64 %x) nounwind {
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; CHECK-LABEL: my_clrbit5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = clrbit(r0,#13)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%and = and i64 %0, -8193
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ret i64 %and
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}
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define i64 @my_clrbit6(i64 %x) nounwind {
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; CHECK-LABEL: my_clrbit6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = clrbit(r1,#27)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%and = and i64 %0, -576460752303423489
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ret i64 %and
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}
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define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
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; CHECK-LABEL: my_setbit:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = setbit(r0,#15)
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memh(r29+#6) = r0
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; CHECK-NEXT: }
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entry:
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%crc.addr = alloca i16, align 2
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store i16 %crc, ptr %crc.addr, align 2
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%0 = load i16, ptr %crc.addr, align 2
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%conv = zext i16 %0 to i32
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%or = or i32 %conv, 32768
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%conv1 = trunc i32 %or to i16
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store i16 %conv1, ptr %crc.addr, align 2
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%1 = load i16, ptr %crc.addr, align 2
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ret i16 %1
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}
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define i32 @my_setbit2(i32 %x) nounwind {
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; CHECK-LABEL: my_setbit2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = setbit(r0,#15)
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; CHECK-NEXT: r1 = r0
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memw(r29+#4) = r1
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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%or = or i32 %0, 32768
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ret i32 %or
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}
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define i64 @my_setbit3(i64 %x) nounwind {
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; CHECK-LABEL: my_setbit3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = setbit(r0,#15)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%or = or i64 %0, 32768
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ret i64 %or
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}
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define i32 @my_setbit4(i32 %x) nounwind {
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; CHECK-LABEL: my_setbit4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = setbit(r0,#31)
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; CHECK-NEXT: r1 = r0
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memw(r29+#4) = r1
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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%or = or i32 %0, -2147483648
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ret i32 %or
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}
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define i64 @my_setbit5(i64 %x) nounwind {
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; CHECK-LABEL: my_setbit5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = setbit(r1,#13)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%or = or i64 %0, 35184372088832
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ret i64 %or
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}
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define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
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; CHECK-LABEL: my_togglebit:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = togglebit(r0,#15)
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memh(r29+#6) = r0
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; CHECK-NEXT: }
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entry:
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%crc.addr = alloca i16, align 2
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store i16 %crc, ptr %crc.addr, align 2
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%0 = load i16, ptr %crc.addr, align 2
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%conv = zext i16 %0 to i32
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%xor = xor i32 %conv, 32768
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%conv1 = trunc i32 %xor to i16
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store i16 %conv1, ptr %crc.addr, align 2
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%1 = load i16, ptr %crc.addr, align 2
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ret i16 %1
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}
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define i32 @my_togglebit2(i32 %x) nounwind {
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; CHECK-LABEL: my_togglebit2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = togglebit(r0,#15)
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; CHECK-NEXT: r1 = r0
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: memw(r29+#4) = r1
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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%xor = xor i32 %0, 32768
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ret i32 %xor
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}
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define i64 @my_togglebit3(i64 %x) nounwind {
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; CHECK-LABEL: my_togglebit3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = togglebit(r0,#15)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%xor = xor i64 %0, 32768
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ret i64 %xor
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}
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define i64 @my_togglebit4(i64 %x) nounwind {
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; CHECK-LABEL: my_togglebit4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: {
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; CHECK-NEXT: r29 = add(r29,#-8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = togglebit(r1,#20)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: r29 = add(r29,#8)
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; CHECK-NEXT: memd(r29+#0) = r1:0
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; CHECK-NEXT: }
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entry:
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%x.addr = alloca i64, align 8
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store i64 %x, ptr %x.addr, align 8
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%0 = load i64, ptr %x.addr, align 8
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%xor = xor i64 %0, 4503599627370496
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ret i64 %xor
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}
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