2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
69 lines
2.3 KiB
LLVM
69 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s
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; This test checks the case if there are more than 2 uses of a constan address, move the
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; value in to a register and replace all instances of constant with the register.
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; The GenMemAbsolute pass generates a absolute-set instruction if there are more
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; than 2 uses of this register.
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; CHECK: loadi32_3
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; CHECK-NOT: r{{[0-9]+}} = memw(##441652)
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; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
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; CHECK:r{{[0-9]+}} = memw(r[[REG:[0-9]+]]=##441652)
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; CHECK-NOT: r{{[0-9]+}} = {emw(##441652)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##441652)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##441652)
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define void @loadi32_3() #0 {
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entry:
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%0 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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%1 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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%2 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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ret void
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}
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; CHECK: loadi32_2
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; CHECK-NOT: r{{[0-9]+}} = ##441652
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; CHECK: r{{[0-9]+}} = memw(##441652)
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; CHECK: r{{[0-9]+}} = memw(##441652)
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define void @loadi32_2() #0 {
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entry:
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%0 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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%1 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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ret void
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}
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; CHECK: loadi32_abs_global_3
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
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; CHECK:r{{[0-9]+}} = memw(r[[REG:[0-9]+]]=##globalInt)
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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@globalInt = external global i32, align 8
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define void @loadi32_abs_global_3() #0 {
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entry:
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%0 = load volatile i32, ptr @globalInt, align 4
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%1 = load volatile i32, ptr @globalInt, align 4
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%2 = load volatile i32, ptr @globalInt, align 4
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ret void
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}
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; CHECK: loadi32_abs_global_2
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; CHECK-NOT:r[[REG:[0-9]+]] = ##globalInt
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; CHECK:r{{[0-9]+}} = memw(##globalInt)
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; CHECK:r{{[0-9]+}} = memw(##globalInt)
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define void @loadi32_abs_global_2() #0 {
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entry:
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%0 = load volatile i32, ptr @globalInt, align 4
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%1 = load volatile i32, ptr @globalInt, align 4
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ret void
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}
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attributes #0 = { nounwind }
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