2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
44 lines
1.9 KiB
LLVM
44 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s
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; CHECK-NOT: vcombine
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define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4, i32 %a5) #0 {
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b0:
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%v1 = load i64, ptr %a1, align 8
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%v2 = shl i64 %v1, 8
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%v3 = trunc i64 %v2 to i32
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%v4 = trunc i64 %v1 to i32
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%v5 = and i32 %v4, 16777215
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%v7 = load <16 x i32>, ptr %a0, align 64
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%v8 = getelementptr inbounds i8, ptr %a0, i32 32
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%v10 = load <16 x i32>, ptr %v8, align 64
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%v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> %v7)
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%v12 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v5, i32 0)
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%v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v3, i32 0)
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%v14 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v12)
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%v15 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v14, <16 x i32> %v14, i32 %a2)
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%v16 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v16, <16 x i32> %v16, i32 %a2)
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%v18 = getelementptr inbounds i8, ptr %a3, i32 32
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store <16 x i32> %v15, ptr %v18, align 64
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store <16 x i32> %v17, ptr %a3, align 64
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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